ST STM32F412

Quad-SPI interface (QUADSPI) RM0402
314/1163 RM0402 Rev 6
12.5.10 QUADSPI polling status mask register (QUADSPI_PSMKR)
Address offset: 0x0024
Reset value: 0x0000 0000
12.5.11 QUADSPI polling status match register (QUADSPI_PSMAR)
Address offset: 0x0028
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MASK[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MASK[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MASK[31:0]: Status mask
Mask to be applied to the status bytes received in polling mode.
For bit n:
0: Bit n of the data received in automatic polling mode is masked and its value is not
considered in the matching logic
1: Bit n of the data received in automatic polling mode is unmasked and its value is
considered in the matching logic
This field can be written only when BUSY = 0.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MATCH[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MATCH[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 MATCH[31:0]: Status match
Value to be compared with the masked status register to get a match.
This field can be written only when BUSY = 0.