RM0402 Rev 6 199/1163
RM0402 Direct memory access controller (DMA)
230
The 8 requests from the peripherals (such as TIM, ADC, SPI, I2C) are independently
connected to each channel and their connection depends on the product implementation.
Table 30 and Table 31 give examples of DMA request mappings.
Table 30. DMA1 request mapping
Peripheral
requests
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
Channel 0 SPI3_RX I2C1_TX SPI3_RX SPI2_RX SPI2_TX SPI3_TX - SPI3_TX
Channel 1 I2C1_RX I2C3_RX TIM7_UP I2CFMP1_RX TIM7_UP I2C1_RX I2C1_TX I2C1_TX
Channel 2 TIM4_CH1 I2CFMP1_TX I2S3_EXT_RX TIM4_CH2 I2S2_EXT_TX I2S3_EXT_TX TIM4_UP TIM4_CH3
Channel 3 I2S3_EXT_RX
TIM2_UP
TIM2_CH3
I2C3_RX I2S2EXT_RX I2C3_TX TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM2_UP
TIM2_CH4
Channel 4 - USART3_RX - USART3_TX - USART2_RX USART2_TX I2CFMP1_TX
Channel 5 - -
TIM3_UP
TIM3_CH4
-
TIM3_CH1
TIM3_TRIG
TIM3_CH2 - TIM3_CH3
Channel 6
TIM5_CH3
TIM5_UP
TIM5_CH4
TIM5_TRIG
TIM5_CH1
TIM5_CH4
TIM5_TRIG
TIM5_CH2 I2C3_TX TIM5_UP USART2_RX
Channel 7 I2CFMP1_RX TIM6_UP I2C2_RX I2C2_RX USART3_TX - - I2C2_TX
Table 31. DMA2 request mapping
Peripheral
requests
Stream 0 Stream 1 Stream 2 Stream 3 Stream 4 Stream 5 Stream 6 Stream 7
Channel 0 ADC1 -
TIM8_CH1
TIM8_CH2
TIM8_CH3
- ADC1 -
TIM1_CH1
TIM1_CH2
TIM1_CH3
-
Channel 1 - - - - - - - -
Channel 2 - - SPI1_TX SPI5_RX SPI5_TX - - -
Channel 3 SPI1_RX
DFSDM1_
FLT1
SPI1_RX SPI1_TX
DFSDM1_
FLT1
SPI1_TX
DFSDM1_
FLT0
QUADSPI
Channel 4 SPI4_RX SPI4_TX USART1_RX SDIO SPI4_RX USART1_RX SDIO USART1_TX
Channel 5 - USART6_RX USART6_RX SPI4_RX SPI4_TX SPI5_TX USART6_TX USART6_TX
Channel 6 TIM1_TRIG TIM1_CH1 TIM1_CH2 TIM1_CH1
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM1_UP TIM1_CH3 -
Channel 7
DFSDM1_
FLT0
TIM8_UP TIM8_CH1 TIM8_CH2 TIM8_CH3 SPI5_RX SPI5_TX
TIM8_CH4
TIM8_TRIG
TIM8_COM
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