Digital filter for sigma delta modulators (DFSDM) RM0402
376/1163 RM0402 Rev 6
14.6 DFSDM DMA transfer
To decrease the CPU intervention, conversions can be transferred into memory using a
DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1
in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting
bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or
regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is
reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register.
14.7 DFSDM channel y registers (y=0..3)
Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register. Write access to DFSDM_CHyDATINR register can be either word access (32-bit)
or half-word access (16-bit).
14.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1)
This register specifies the parameters used by channel y.
Address offset: 0x00 + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000
Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE
Analog watchdog
AWDF,
AWHTF[3:0],
AWLTF[3:0]
writing CLRAWHTF[3:0] = 1
writing CLRAWLTF[3:0] = 1
AWDIE,
(AWDCH[3:0])
short-circuit detector SCDF[3:0] writing CLRSCDF[3:0] = 1
SCDIE,
(SCDEN)
Channel clock absence CKABF[3:0] writing CLRCKABF[3:0] = 1
CKABIE,
(CKABEN)
Table 90. DFSDM interrupt requests (continued)
Interrupt event Event flag
Event/Interrupt clearing
method
Interrupt enable
control bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM
EN
CKOUT
SRC
Res. Res. Res. Res. Res. Res. CKOUTDIV[7:0]
rw rw rw rw rw rw rw rw rw rw
1514131211109876543210
DATPACK[1:0] DATMPX[1:0] Res. Res. Res.
CHIN
SEL
CHEN
CKAB
EN
SCDEN Res. SPICKSEL[1:0] SITP[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw
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