Analog-to-digital converter (ADC) RM0402
332/1163 RM0402 Rev 6
13.11 ADC interrupts
An interrupt can be produced on the end of conversion for regular and injected groups,
when the analog watchdog status bit is set and when the overrun status bit is set. Separate
interrupt enable bits are available for flexibility.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
• JSTRT (Start of conversion for channels of an injected group)
• STRT (Start of conversion for channels of a regular group)
Table 79. ADC interrupts
Interrupt event Event flag Enable control bit
End of conversion of a regular group EOC EOCIE
End of conversion of an injected group JEOC JEOCIE
Analog watchdog status bit is set AWD AWDIE
Overrun OVR OVRIE
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