ST STM32F412 User Manual

Interrupts and events RM0402
236/1163 RM0402 Rev 6
10.2.2 EXTI block diagram
Figure 29 shows the block diagram.
Figure 29. External interrupt/event controller block diagram
10.2.3 Wakeup event management
The STM32F4xx are able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex
®
-M4 with FPU System Control register. When the
MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
• or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
To use an external line as a wakeup event, refer to Section 10.2.4: Functional description.
Peripheral interface
Edge detect
circuit
AMBA APB bus
PCLK2
23
23 23
2323
23
23
To NVIC interrupt
controller
Software
interrupt
event
register
Rising
trigger
selection
register
23
Event
mask
register
Pulse
generator
23
23
23
23
Input
line
Pending
request
register
23
MS32662V1
Interrupt
mask
register
Falling
trigger
selection
register

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English