Direct memory access controller (DMA) RM0402
204/1163 RM0402 Rev 6
Figure 27. Memory-to-memory mode
1. For double-buffer mode.
9.3.8 Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented or kept
constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR
register.
Disabling the increment mode is useful when the peripheral source or destination data is
accessed through a single register.
If the increment mode is enabled, the address of the next transfer is the address of the
previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on
the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.
In order to optimize the packing operation, it is possible to fix the increment offset size for
the peripheral address whatever the size of the data transferred on the AHB peripheral port.
The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with
the data size on the peripheral AHB port, or on a 32-bit address (the address is then
incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.
If the PINCOS bit is set, the address of the following transfer is the address of the previous
one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE
value. The AHB memory port, however, is not impacted by this operation.
Memory bus
Peripheral bus
Stream enable
Arbiter
DMA_SxM1AR
(1)
FIFO
AHB memory
port
AHB peripheral
port
DMA_SxPAR
FIFO
level
DMA controller
DMA_SxM0AR
destination
source
Memory 1
Memory 2
FIFO
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