ST STM32F412 User Manual

Power controller (PWR) RM0402
94/1163 RM0402 Rev 6
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
5.3.1 Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 6.3.3: RCC clock configuration register (RCC_CFGR).
5.3.2 Peripheral clock gating
In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register
(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR) (see
Section 6.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR),
Section 6.3.11: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) and
Section 6.3.12: RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
Table 15. Low-power mode summary
Mode name Entry Wakeup
Effect on 1.2 V
domain clocks
Effect on
V
DD
domain
clocks
Voltage regulator
Sleep and
BAM
(1)
(Sleep now or
Sleep-on-
exit)
WFI or Return
from ISR
Any interrupt
CPU CLK OFF
no effect on other
clocks or analog
clock sources
None ON
WFE Wakeup event
Stop
SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
Any EXTI line (configured
in the EXTI registers,
internal and external lines)
All 1.2 V domain
clocks OFF
HSI and
HSE
oscillator
s OFF
Main regulator or
Low-Power
regulator (depends
on PWR power
control register
(PWR_CR)
Standby
PDDS bit +
SLEEPDEEP bit
+ WFI, Return
from ISR or WFE
WKUP pin rising edge,
RTC alarm (Alarm A or
Alarm B), RTC Wakeup
event, RTC tamper
events, RTC time stamp
event, external reset in
NRST pin, IWDG reset
OFF
1. Refer to Section 5.3.4: Batch acquisition mode for specific BAM entry and exit requirements.

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English