ST STM32F412 User Manual

Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmit-
790/1163 RM0402 Rev 6
Figure 258. USART data clock timing diagram (M=1)
Figure 259. RX data setup/hold time
Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.
25.4.10 Single-wire half-duplex communication
The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
• LINEN and CLKEN bits in the USART_CR2 register,
• SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single-wire half-duplex protocol where the TX and
RX lines are internally connected. The selection between half- and full-duplex
communication is made with a control bit ‘HALF DUPLEX SEL’ (HDSEL in USART_CR3).
MSv34710V1
0 1 2 3 4 5 6 8
0 1 2 3 4 5 6 8
*
*
*
*
MSB
MSB
LSB
LSBStart
Start Stop
Idle or
preceding
transmission
Idle or next
transmission
*
*LBCL bit controls last data pulse
Capture
strobe
Data on RX
(from slave)
Data on TX
(from master)
Clock (CPOL=1,
CPHA=1)
Clock (CPOL=1,
CPHA=0)
Clock (CPOL=0,
CPHA=1)
Clock (CPOL=0,
CPHA=0)
Stop
M bits =01 (9 data bits)
7
7
MSv31161V1
Data on RX (from slave)
SCLK
(capture strobe on SCLK
rising edge in this example)
Valid DATA bit
t
SETUP
t
HOLD
t
SETUP=
t
HOLD
1/16 bit time

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English