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ST STM32F412 User Manual

ST STM32F412
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USB on-the-go full-speed (OTG_FS) RM0402
1018/1163 RM0402 Rev 6
Device mode
29.15.14 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS)
Address offset: 0x02C
Reset value: 0x0008 0200
Note: In device mode, this register is not valid.
This read-only register contains the free space information for the non-periodic Tx FIFO and
the non-periodic transmit request queue.
Bits 31:16 TX0FD: Endpoint 0 Tx FIFO depth
This value is in terms of 32-bit words.
Minimum value is 16
Programmed values must respect the available FIFO memory allocation and must not
exceed the power-on value.
Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address
This field configures the memory start address for the endpoint 0 transmit FIFO RAM.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. NPTXQTOP[6:0] NPTQXSAV[7:0]
rrrrrrrrrrrrrrr
1514131211109876543210
NPTXFSAV[15:0]
rrrrrrrrrrrrrrrr

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ST STM32F412 Specifications

General IconGeneral
BrandST
ModelSTM32F412
CategoryMicrocontrollers
LanguageEnglish

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