RM0402 Rev 6 395/1163
RM0402 Digital filter for sigma delta modulators (DFSDM)
400
14.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)
Address offset: 0x138 + 0x80 * x, (x = 0 to 1)
Reset value: 0x0000 0000
Bits 31:8 EXMIN[23:0]: Extremes detector minimum value
These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx.
EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 EXMINCH[1:0]: Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits
are cleared by reading of this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNVCNT[27:12]
rrrrrrrrrrrrrrrr
1514131211109876543210
CNVCNT[11:0] Res. Res. Res. Res.
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Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / f
DFSDMCLK
The timer has an input clock from DFSDM clock (system clock f
DFSDMCLK
). Conversion time
measurement is started on each conversion start and stopped when conversion finishes (interval
between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion
time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [F
OSR
* (I
OSR
-1 + F
ORD
) + F
ORD
] / f
CKIN
..... for Sinc
x
filters
t = [F
OSR
* (I
OSR
-1 + 4) + 2] / f
CKIN
..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [F
OSR
* I
OSR
] / f
CKIN
in case if F
OSR
= FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = I
OSR
/ f
CKIN
)
where: f
CKIN
is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input (from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also
this interruption time.
Bits 3:0 Reserved, must be kept at reset value.
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