Flexible static memory controller (FSMC) RM0402
270/1163 RM0402 Rev 6
WAIT management in asynchronous accesses
If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:
3:2 MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM)
1 MUXEN 0x1
0 MBKEN 0x1
Table 65. FSMC_BTRx bitfields (Muxed mode)
Bit number Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST
Duration of the second access phase (DATAST HCLK cycles for read
accesses and DATAST+1 HCLK cycles for write accesses).
7:4 ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
3:0 ADDSET
Duration of the first access phase (ADDSET HCLK cycles). Minimum
value for ADDSET is 1.
Table 64. FSMC_BCRx bitfields (Muxed mode) (continued)
Bit number Bit name Value to set
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