Fast-mode Plus Inter-integrated circuit (FMPI2C) interface RM0402
660/1163 RM0402 Rev 6
23.4.4 Mode selection
The interface can operate in one of the four following modes:
• Slave transmitter
• Slave receiver
• Master transmitter
• Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.
Communication flow
In Master mode, the FMPI2C interface initiates a data transfer and generates the clock
signal. A serial data transfer always begins with a START condition and ends with a STOP
condition. Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the general call address. The general call address detection can be enabled or disabled by
software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.
Figure 209. I
2
C bus protocol
Acknowledge can be enabled or disabled by software. The FMPI2C interface addresses can
be selected by software.
23.4.5 FMPI2C initialization
Enabling and disabling the peripheral
The FMPI2C peripheral clock must be configured and enabled in the clock controller.
Then the FMPI2C can be enabled by setting the PE bit in the FMPI2C_CR1 register.
MS19854V1
SDA
SCL
Start
condition
Stop
condition
MSB ACK
12 89
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