Flexible static memory controller (FSMC) RM0402
250/1163 RM0402 Rev 6
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
11.6 NOR Flash/PSRAM controller
The FSMC generates the appropriate signal timings to drive the following types of
memories:
• Asynchronous SRAM and ROM
– 8 bits
– 16 bits
• PSRAM (CellularRAM™)
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
• NOR Flash memory
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
The FSMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FSMC supports a wide range of devices through a programmable timings among
which:
• Programmable wait states (up to 15)
• Programmable bus turnaround cycles (up to 15)
• Programmable output enable and write enable delays (up to 15)
• Independent read and write timings and protocol to support the widest variety of
memories and timings
• Programmable continuous clock (FSMC_CLK) output.
The FSMC Clock (FSMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
1. HADDR are internal AHB address lines that are translated to external memory.
Table 43. NOR/PSRAM External memory address
Memory width
(1)
1. In case of a 16-bit external memory width, the FSMC internally uses HADDR[25:1] to generate the address
for external memory FSMC_A[24:0].
Whatever the external memory width, FSMC_A[0] should be connected to external memory address A[0].
Data address issued to the memory Maximum memory capacity (bits)
8-bit HADDR[25:0] 64 Mbytes x 8 = 512 Mbit
16-bit HADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit
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