ST STM32F412 - Hardware Flow Control; Figure 265. Reception Using DMA; Figure 266. Hardware Flow Control between 2 Usarts

RM0402 Rev 6 797/1163
RM0402 Universal synchronous receiver transmitter (USART) /universal asynchronous receiver
810
Figure 265. Reception using DMA
Error flagging and interrupt generation in multibuffer communication
In case of multibuffer communication if any error occurs during the transaction the error flag
will be asserted after the current byte. An interrupt will be generated if the interrupt enable
flag is set. For framing error, overrun error and noise flag that are asserted with RXNE in
case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in
the USART_CR3 register), which if set will issue an interrupt after the current byte with
either of these errors.
25.4.14 Hardware flow control
It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The
Figure 266 shows how to connect 2 devices in this mode:
Figure 266. Hardware flow control between 2 USARTs
RTS and CTS flow control can be enabled independently by writing respectively RTSE and
CTSE bits to 1 (in the USART_CR3 register).
TX line
Frame 1
F2
F3
Set by hardware
cleared by DMA read
F1
ai17193c
Frame 2
Frame 3
RXNE flag
USART_TDR
DMA request
DMA reads
USART_TDR
DMA TCIF flag
(transfer complete)
Software configures the
DMA to receive 3 data
blocks and enables
the USART
DMA reads F3
from USART_TDR
The DMA transfer
is complete
(TCIF=1 in
DMA_ISR)
Set by hardware
Cleared
by
software
DMA reads F2
from USART_TDR
DMA reads F1
from USART_TDR
MSv31169V1
TX circuit
USART 1
TX
RX circuit
RX circuit
USART 2
TX circuit
TX
nCTS
nCTS
nRTS
RX
nRTS
RX