EasyManuals Logo

ST STM32F412 User Manual

ST STM32F412
1163 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #362 background imageLoading...
Page #362 background image
Digital filter for sigma delta modulators (DFSDM) RM0402
362/1163 RM0402 Rev 6
Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sinc
x
filters (x=1..5):
t = CNVCNT/f
DFSDMCLK
= [F
OSR
* (I
OSR
-1 + F
ORD
) + F
ORD
] / f
CKIN
for FastSinc filter:
t = CNVCNT/f
DFSDMCLK
= [F
OSR
* (I
OSR
-1 + 4) + 2] / f
CKIN
regular conversion with FAST = 1 (except first conversion):
for Sinc
x
and FastSinc filters:
t = CNVCNT/f
DFSDMCLK
= [F
OSR
* I
OSR
] / f
CKIN
in case if F
OSR
= FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = I
OSR
/ f
CKIN
(... but CNVCNT=0)
where:
f
CKIN
is the channel input clock frequency (on given channel CKINy pin) or input data
rate (in case of parallel data input)
F
OSR
is the filter oversampling ratio: F
OSR
= FOSR[9:0]+1 (see DFSDM_FLTxFCR
register)
I
OSR
is the integrator oversampling ratio: I
OSR
= IOSR[7:0]+1 (see DFSDM_FLTxFCR
register)
F
ORD
is the filter order: F
ORD
= FORD[2:0] (see DFSDM_FLTxFCR register)
Channel offset setting
Each channel has its own offset setting (in register) which is finally subtracted from each
conversion result (injected or regular) from a given channel. Offset correction is performed
after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0]
field in DFSDM_CHyCFGR2 register.
Data right bit shift
To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts
which will be applied on each conversion result (injected or regular) from a given channel.
The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is
maintained, in order to have valid 24-bit signed format of result data.

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the ST STM32F412 and is the answer not in the manual?

ST STM32F412 Specifications

General IconGeneral
BrandST
ModelSTM32F412
CategoryMicrocontrollers
LanguageEnglish

Related product manuals