ST STM32F412 User Manual

List of figures RM0402
38/1163 RM0402 Rev 6
Figure 49. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 275
Figure 50. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 277
Figure 51. QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 288
Figure 52. QUADSPI block diagram when dual-flash mode is enabled . . . . . . . . . . . . . . . . . . . . . . 289
Figure 53. An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 54. An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 55. nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 56. nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 57. nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 58. nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 59. Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 60. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 61. Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Figure 62. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
Figure 63. Right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 64. Left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 65. Left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Figure 66. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 330
Figure 67. Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 68. Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 69. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Figure 70. Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 71. Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 72. First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . . 361
Figure 73. DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . . 364
Figure 74. Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 75. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Figure 76. Entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Figure 77. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
Figure 78. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 416
Figure 79. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 416
Figure 80. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 81. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 82. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 83. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 84. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Figure 85. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Figure 86. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Figure 87. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Figure 88. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 89. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Figure 90. Counter timing diagram, update event when repetition counter is not used. . . . . . . . . . . 423
Figure 91. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 424
Figure 92. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Figure 93. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 425
Figure 94. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Figure 95. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 426
Figure 96. Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 426
Figure 97. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 427
Figure 98. Control circuit in normal mode, internal clock divided by 1. . . . . . . . . . . . . . . . . . . . . . . . 428

ST STM32F412 Specifications

General

Brand	ST
Model	STM32F412
Category	Microcontrollers
Language	English