Freescale Semiconductor MPC5604B - Page 213

MPC5604B/C Microcontroller Reference Manual, Rev. 8
202 Freescale Semiconductor
9.3.1.8 STANDBY Reset Sequence Register (RGM_STDBY)
This register defines the reset sequence to be applied on STANDBY mode exit. It can be accessed in
read/write in either supervisor mode or test mode. It can be accessed in read only in user mode.
NOTE
This register is reset on any enabled ‘destructive’ or ‘functional’ reset event.
9.3.1.9 Functional Bidirectional Reset Enable Register (RGM_FBRE)
This register enables the generation of an external reset on functional reset. It can be accessed in read/write
in either supervisor mode or test mode. It can be accessed in read in user mode.
Address 0xC3FE_401A Access: Supervisor read/write
0123456789101112131415
R
00000000
BOOT_FROM_BKP_RAM
0000000
W
reset0000000000000000
Figure 9-9. STANDBY Reset Sequence Register (RGM_STDBY)
Table 9-10. STANDBY Reset Sequence Register (RGM_STDBY) Field Descriptions
Field Description
BOOT_
FROM_
BKP_RAM
Boot from Backup SRAM indicator — This bit indicates whether the system will boot from backup
SRAM or flash out of STANDBY exit.
0 Boot from default boot location on STANDBY exit
1 Boot from backup SRAM on STANDBY exit
Address 0xC3FE_401C Access: Supervisor read/write
0123456789101112131415
R
BE_EXR
000000
BE_FLASH
BE_LVD45
BE_CMU_FHL
BE_CMU_OLR
BE_FMPLL
BE_CHKSTOP
BE_SOFT
BE_CORE
BE_JTAG
W
POR0000000000000000
Figure 9-10. Functional Bidirectional Reset Enable Register (RGM_FBRE)