Freescale Semiconductor MPC5604B - Page 458

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 447
22.3.4.9 Interrupt Masks 2 Register (IMASK2)
This register allows any number of a range of 32 Message Buffer Interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (i.e. when the corresponding IFLAG2 bit is set).
BOFF_INT Bus Off’ Interrupt
This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control
Register (BOFF_MSK) is set, an interrupt is generated to the CPU. This bit is cleared by writing it
to ‘1’. Writing ‘0’ has no effect.
1 = FlexCAN module entered ‘Bus Off’ state
0 = No such occurrence
ERR_INT Error Interrupt
This bit indicates that at least one of the Error Bits (bits 16–21) is set. If the corresponding mask bit
in the Control Register (ERR_MSK) is set, an interrupt is generated to the CPU. This bit is cleared
by writing it to ‘1’.Writing ‘0’ has no effect.
1 = Indicates setting of any Error Bit in the Error and Status Register
0 = No such occurrence
Table 22-13. Fault confinement state
Value Meaning
00 Error Active
01 Error Passive
1X Bus Off
Offset: 0x0024 Access: Read/write
0123456789101112131415
R
BUF
63M
BUF
62M
BUF
61M
BUF
60M
BUF
59M
BUF
58M
BUF
57M
BUF
56M
BUF
55M
BUF
54M
BUF
53M
BUF
52M
BUF
51M
BUF
50M
BUF
49M
BUF
48M
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BUF
47M
BUF
46M
BUF
45M
BUF
44M
BUF
43M
BUF
42M
BUF
41M
BUF
40M
BUF
39M
BUF
38M
BUF
37M
BUF
36M
BUF
35M
BUF
34M
BUF
33M
BUF
32M
W
Reset0000000000000000
Figure 22-11. Interrupt Masks 2 Register (IMASK2)
Table 22-12. ESR field descriptions (continued)
Field Description