Freescale Semiconductor MPC5604B - Page 561

MPC5604B/C Microcontroller Reference Manual, Rev. 8
550 Freescale Semiconductor
Figure 24-20. SAOC example with EDPOL value being transferred to the output flip-flop
Figure 24-21. SAOC example toggling the output flip-flop
Figure 24-22. SAOC example with flag behavior
24.4.4.1.1.4 Input Pulse Width Measurement (IPWM) Mode
The IPWM mode (MODE[0:6] = 0000100) allows the measurement of the width of a positive or negative
pulse by capturing the leading edge on register B1 and the trailing edge on register A2. Successive captures
are done on consecutive edges of opposite polarity. The leading edge sensitivity (that is, pulse polarity) is
selected by EDPOL bit in the EMIOSC[n] register. Registers EMIOSA[n] and EMIOSB[n] return the
values in register A2 and B1, respectively.
The capture function of register A2 remains disabled until the first leading edge triggers the first input
capture on register B2. When this leading edge is detected, the count value of the selected time base is
latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the
selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000
output flip-flop
Update to A1
A1 value
1
0xxxxxxx 0x001000
FLAG pin/register
0x001000 0x001000 0x001000
A1 match
A1 match A1 match
Notes: 1. EMIOSA[n] = A2
EDSEL = 0
EDPOL = 1
A2 = A1 according to OU[n] bit
selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000
A1 value
1
0xxxxxxx 0x001000
output flip-flop
Update to A1
FLAG pin/register
A1 match
A1 match A1 match
0x001000 0x001000
0x001000
Notes: 1. EMIOSA[n] = A2
EDSEL = 1
EDPOL = x
A2 = A1 according to OU[n] bit
selected counter bus 0x0 0x2
FLAG set event
A2 value
1
0x1
output flip-flop
Note: 1. EMIOSA[n] <= A2
0x0 0x20x1 0x2 0x0 0x10x1
FLAG pin/register
FLAG clear
EDSEL = 1
System Clock
A1 match
EDPOL = x