MPC5604B/C Microcontroller Reference Manual, Rev. 8
556 Freescale Semiconductor
When in up count mode, a match between the internal counter and register A1 sets the FLAG and clears
the internal counter. The timing of those events varies according to the MC mode setup as follows:
• Internal counter clearing on match start (MODE[0:6] = 001000b)
— External clock is selected if MODE[6] is set. In this case the internal counter clears as soon as
the match signal occurs. The channel FLAG is set at the same time the match occurs. Note that
by having the internal counter cleared as soon as the match occurs and incremented at the next
input event a shorter zero count is generated. See Figure 24-52 and Figure 24-53.
— Internal clock source is selected if MODE[6] is cleared. In this case the counter clears as soon
as the match signal occurs. The channel FLAG is set at the same time the match occurs. At the
next prescaler tick after the match the internal counter remains at zero and only resumes
counting on the following tick. See Figure 24-52 and Figure 24-54.
• Internal counter clearing on match end (MODE[0:6] = 001001b)
— External clock is selected if MODE[6] is set. In this case the internal counter clears when the
match signal is asserted and the input event occurs. The channel FLAG is set at the same time
the counter is cleared. See Figure 24-52 and Figure 24-55.
— Internal clock source is selected if MODE[6] is cleared. In this case the internal counter clears
when the match signal is asserted and the prescaler tick occurs. The channel FLAG is set at the
same time the counter is cleared. See Figure 24-52 and Figure 24-55.
NOTE
If the internal clock source is selected and the prescaler of the internal
counter is set to ‘1’, the MC mode behaves the same way even in Clear on
Match Start or Clear on Match End submodes.
When in up/down count mode (MODE[0:6] = 00101bb), a match between the internal counter and register
A1 sets the FLAG and changes the counter direction from increment to decrement. A match between
register B1 and the internal counter changes the counter direction from decrement to increment and sets
the FLAG only if MODE[5] bit is set.
Only values different than 0x0 must be written at A register. Loading 0x0 leads to unpredictable results.
Updates on A register or counter in MC mode may cause loss of match in the current cycle if the transfer
occurs near the match. In this case, the counter may rollover and resume operation in the next cycle.
Register B2 has no effect in MC mode. Nevertheless, register B2 can be accessed for reads and writes by
addressing EMIOSB.
Figure 24-30 and Figure 24-31 show how the Unified Channel can be used as modulus counter in up mode
and up/down mode, respectively.
To Next Page
Loading...
