Freescale Semiconductor MPC5604B - Page 576

MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 565
Figure 24-40 describes the load of A1 and B1 registers which occurs when the selected counter bus
transitions from 0x2 to 0x1. This event defines the cycle boundary. Note that values written to A2 or B2
within cycle n are loaded into A1 or B1 registers, respectively, and used to generate matches in cycle n+1.
Figure 24-40. OPWMCB A1 and B1 registers load
Bit OU[n] of the EMIOSOUDIS register can be used to disable the A1 and B1 updates, thus allowing to
synchronize the load on these registers with the load of A1 or B1 registers in others channels. Note that
using the update disable bit A1 and B1 registers can be updated at the same counter cycle thus allowing to
change both registers at the same time.
In this mode A1 matches always sets the internal counter to 0x1. When operating with leading edge dead
time insertion the first A1 match sets the internal counter to 0x1. When a match occurs between register
B1 and the internal time base, the output flip-flop is set to the value of the EDPOL bit. In the following
match between register A1 and the selected time base, the output flip-flop is set to the complement of the
EDPOL bit. This sequence repeats continuously. The internal counter should not reach 0x0 as consequence
of a rollover. In order to avoid it the user should not write to the EMIOSB register a value greater than
twice the difference between external count up limit and EMIOSA value.
Figure 24-41 shows two cycles of a Center Aligned PWM signal. Note that both A1 and B1 register values
are changing within the same cycle which allows to vary at the same time the duty cycle and dead time
values.
A1 value
0x000020
A2 value
0x000020
0x000015
0x000016
0x000015
A1/B1 load signal
Selected Counter == 2
Selected
TIME
write to A2
write to B2
write to B2
write to A2
0x000001
0x000005
0x000006
0x000016
cycle n
cycle n+1
cycle n+2
Counter Bus
B1 value
0x000004
B2 value
0x000004
0x000005
0x000006
0x000005
0x000006
Prescaler ratio = 2
System Clock