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ST STM32F412 User Manual

ST STM32F412
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RM0402 Rev 6 27/1163
RM0402 Contents
31
29.6.3 Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
29.7 OTG_FS as a USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
29.7.1 SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
29.7.2 USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
29.7.3 Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
29.7.4 Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
29.8 OTG_FS SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
29.8.1 Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
29.8.2 Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
29.9 OTG_FS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
29.10 OTG_FS Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . . 985
29.11 OTG_FS data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
29.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
29.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
29.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
29.12 OTG_FS system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
29.13 OTG_FS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
29.14 OTG_FS control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
29.14.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
29.15 OTG_FS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
29.15.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . . 997
29.15.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 1000
29.15.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 1001
29.15.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 1002
29.15.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 1004
29.15.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 1006
29.15.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 1010
29.15.8 OTG receive status debug read register (OTG_GRXSTSR) . . . . . . . 1013
29.15.9 OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . . 1014
29.15.10 OTG status read and pop registers (OTG_GRXSTSP) . . . . . . . . . . . 1015
29.15.11 OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . 1016
29.15.12 OTG receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 1017
29.15.13 OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
29.15.14 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018

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ST STM32F412 Specifications

General IconGeneral
BrandST
ModelSTM32F412
CategoryMicrocontrollers
LanguageEnglish

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