Freescale Semiconductor MPC5604B - Page 161

MPC5604B/C Microcontroller Reference Manual, Rev. 8
150 Freescale Semiconductor
8.3.1.5 Interrupt Mask Register (ME_IM)
This register controls whether an event generates an interrupt or not.
Address 0xC3FD_C010 Access: Supervisor read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000
M_ICONF
M_IMODE
M_SAFE
M_MTC
W
Reset0000000000000000
Figure 8-6. Interrupt Mask Register (ME_IM)
Table 8-8. Interrupt Mask Register (ME_IM) Field Descriptions
Field Description
M_ICONF Invalid mode configuration interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_IMODE Invalid mode interrupt mask
0 Invalid mode interrupt is masked
1 Invalid mode interrupt is enabled
M_SAFE SAFE mode interrupt mask
0 SAFE mode interrupt is masked
1 SAFE mode interrupt is enabled
M_MTC Mode transition complete interrupt mask
0 Mode transition complete interrupt is masked
1 Mode transition complete interrupt is enabled