MPC5604B/C Microcontroller Reference Manual, Rev. 8
482 Freescale Semiconductor
DT Delay after Transfer Scaler
The DT field selects the Delay after Transfer Scaler. This field is only used in Master Mode. The Delay
after Transfer is the time between the negation of the PCS signal at the end of a frame and the assertion
of PCS at the beginning of the next frame. Table 23-16 lists the scaler values. In the Continuous Serial
Communications Clock operation the DT value is fixed to one TSCK. The Delay after Transfer is a
multiple of the system clock period and it is computed according to the following equation:
Eqn. 23-3
See Section 23.6.4.4, Delay after transfer (tDT),” for more details.
BR Baud Rate Scaler
The BR field selects the scaler value for the baud rate. This field is only used in Master Mode. The
prescaled system clock is divided by the Baud Rate Scaler to generate the frequency of the SCK.
Table 23-17 lists the Baud Rate Scaler values.The baud rate is computed according to the following
equation:
Eqn. 23-4
See Section 23.6.4.2, CS to SCK delay (tCSC),” for more details.
Table 23-6. DSPI SCK duty cycle
DBR CPHA PBR SCK duty cycle
0 any any 50/50
1 0 00 50/50
1 0 01 33/66
1 0 10 40/60
1 0 11 43/57
1 1 00 50/50
1 1 01 66/33
1 1 10 60/40
1 1 11 57/43
Table 23-7. DSPI transfer frame size
FMSZ Frame size FMSZ Frame size
0000 Reserved 1000 9
0001 Reserved 1001 10
0010 Reserved 1010 11
0011 4 1011 12
0100 5 1100 13
0101 6 1101 14
Table 23-5. DSPIx_CTARn field descriptions (continued)
Field Descriptions
t
DT
1
f
SYS
-----------
PDT DT=
SCK baud rate
f
SYS
PBR
------------
1DBR+
BR
----------------------
=
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