MPC5604B/C Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor 559
Figure 24-33. Modulus Counter Buffered (MCB) Up/Down mode
Figure 24-34 describes in more detail the A1 register update process in up counter mode. The A1 load
signal is generated at the last system clock period of a counter cycle. Thus, A1 is updated with A2 value
at the same time that the counter (EMIOSCNT[n]) is loaded with 0x1. The load signal pulse has the
duration of one system clock period. If A2 is written within cycle n its value is available at A1 at the first
clock of cycle n+1 and the new value is used for match at cycle n+1. The update disable bits OU[n] of
EMIOSOUDIS register can be used to control the update of this register, thus allowing to delay the A1
register update for synchronization purposes.
Figure 24-34. MCB Mode A1 Register Update in Up Counter mode
Figure 24-35 describes the A1 register update in up/down counter mode. Note that A2 can be written at
any time within cycle n in order to be used in cycle n+1. Thus A1 receives this new value at the next cycle
boundary. Note that the update disable bits OU[n] of EMIOSOUDIS register can be used to disable the
update of A1 register.
EMIOSCNT[n]
TIME
write to A2
match A1
match A1
write to A2
0x000001
0x000005
0x000006
0x000007
FLAG set event
A1 value
0x000006 0x000005 0x000007
0x000005 0x000007
A2 value
FLAG pin/register
Prescaler ratio = 1
cycle n+1
cycle n+2cycle n
FLAG clear
A1 value
0x000008
0x000008
0x000001
internal counter
0x000004
0x000006
A2 value
0x000008 0x000004
0x000006
0x000002
0x000004
0x000006
write to A2 write to A2
Match A1
Match A1
A1 load signal
8
4
6
Match A1
Counter = A1
Time
cycle n
cycle n+1
cycle n+2
Prescaler ratio = 2
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