MPC5604B/C Microcontroller Reference Manual, Rev. 8
916 Freescale Semiconductor
LIN Controller Updated Section 20.3.1, “LIN mode features”
Added names for Example 1 and Example 2
Replaced LINFlex memory map
Section 20.8.2, “Register description”
– Aligned hexidecimal reset values to reset values shown in bitmaps where necessary
– Aligned bit numbering in register field description tables to numbering in register bitmaps
where necessary
LIN control register 1 (LINCR1):
– Changed reset value from 0x0082_0000 to 0x0000_0082
– Changed access from w1c to R/W for fields CCD, CFD, LASE, AWUM, MBL[0:3], BF,
SFTM, LBKM, MME, SBDT, RBLM, SLEEP and INIT
LIN interrupt enable register (LINIER):
– Updated LSIE field description
– Changed access from w1c to R/W for fields SZIE, OCIE, BEIE, CEIE, HEIE, FEIE, BOIE,
LSIE, WUIE, DBFIE, DBEIE, DRIE, DTIE and HRIE
Section 20.8.2.3, “LIN status register (LINSR)”: Updated LINS field description; changed
access from w1c to read-only for field RPS
Section 20.8.2.4, “LIN error status register (LINESR)”: Updated SZF field description
UART mode control register (UARTCR): Changed access from w1c to R/W for fields RXEN,
TXEN, OP, PCE, WL and UART
UARTSR field descriptions: Added footnote 1
LIN timeout control status register (LINTCSR): Changed access from w1c to R/W for fields
LTOM, IOT and TOCE
LIN output compare register (LINOCR): Changed access from w1c to R/W for OCx
Section 20.8.2.9, “LIN timeout control register (LINTOCR)”: Updated HTO field description
LIN fractional baud rate register (LINFBRR): Changed access from w1c to R/W for DIV_F
LIN integer baud rate register (LINIBRR): Changed access from w1c to R/W for DIV_M
LIN checksum field register (LINCFR): Changed access from w1c to R/W for CF
LIN control register 2 (LINCR2):
– Changed access from w1c to R/W for fields IOBE and IOPE
– Changed access from w1c to write-only for fields WURQ, DDRQ, DTRQ, ABRQ and
HTRQ
Section 21.7.1.14, “Buffer identifier register (BIDR): Updated CCS field description;
changed access from w1c to R/W for fields DIR and CCS
Buffer data register LSB (BDRL): Changed access from w1c to R/W for DATAx
Section 21.7.1.17, “Identifier filter enable register (IFER): Updated description of
FACT[0:7]; added IFER[FACT] configuration table
Section 21.7.1.18, “Identifier filter match index (IFMI): Replaced IFMI[0 with IFMI[0:4]
Section 21.7.1.19, “Identifier filter mode register (IFMR): Replaced IFM[0:3] with IFM[0:7];
added IFMR[IFM] configuration table; changed register access from User read-only to User
read/write; changed access from read-only to R/W for IFM[0:7]
Section 21.7.1.20, “Identifier filter control register (IFCR2n): Amended address offsets;
changed access from w1c to R/W for fields DIR and CCS
Section 21.7.1.21, “Identifier filter control register (IFCR2n + 1): Amended address offsets;
changed access from w1c to R/W for fields DIR and CCS
Register map and reset values:
– Updated bits of IFMI and IFMR
– Amended address offsets for IFCR2n and for IFCR2n+1
Added Section 21.8.1.4, “Clock gating to Section 21.8.1, “UART mode
Section 21.8.2, “LIN mode: Added footnote regarding slave mode
Updated Section 21.8.2.1.3, “Data reception (transceiver as subscriber)
Table B-4. Changes between revisions 2 and 4 (continued)
Chapter Description
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