RM0402 Rev 6 105/1163
RM0402 Power controller (PWR)
108
Bit 12 Reserved, must be kept at reset value.
Bit 11 MRLVDS: Main regulator Low Voltage in Deep Sleep
0: Main regulator in Voltage scale 3 when the device is in Stop mode.
1: Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is
in Stop mode.
Bit 10 LPLVDS: Low-power regulator Low Voltage in Deep Sleep
0: Low-power regulator on if LPDS bit is set when the device is in Stop mode.
1: Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is
set when device is in Stop mode.
Bit 9 FPDS: Flash power-down in Stop mode
When set, the Flash memory enters power-down mode when the device enters Stop mode.
This allows to achieve a lower consumption in stop mode but a longer restart time.
0: Flash memory not in power-down when the device is in Stop mode
1: Flash memory in power-down when the device is in Stop mode
Bit 8 DBP: Disable backup domain write protection
In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This
bit must be set to enable write access to these registers.
0: Access to RTC and RTC Backup registers.
1: Access to RTC and RTC Backup registers.
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
000: 2.2 V
001: 2.3 V
010: 2.4 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect.
1: Clear the SBF Standby Flag (write).
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect.
1: Clear the WUF Wakeup Flag after 2 System clock cycles.
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