RM0402 Rev 6 149/1163
RM0402 Reset and clock control (RCC) for STM32F412xx
166
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPILPEN: QUADSPI memory controller module clock enable during Sleep mode
Set and cleared by software.
0: QUADSPI module clock disabled during Sleep mode
1: QUADSPI module clock enabled during Sleep mode
Bit 0 FSMCLPEN: Flexible memory controller module clock enable during Sleep mode
Set and cleared by software.
0: FSMC clock disabled during Sleep mode
1: FSMC clock enabled during Sleep mode
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