Flexible static memory controller (FSMC) RM0402
280/1163 RM0402 Rev 6
Bit 19 CBURSTRW: Write burst enable
For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write
operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FSMC_BCRx
register.
0: Write operations are always performed in Asynchronous mode.
1: Write operations are performed in Synchronous mode.
Bits 18:16 CPSIZE[2:0]: CRAM page size
These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address
boundaries between pages. When these bits are configured, the FSMC controller splits
automatically the burst access when the memory page size is reached (refer to memory datasheet
for page size).
000: No burst split when crossing page boundary (default after reset)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
Others: reserved
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
This bit enables/disables the FSMC to use the wait signal even during an asynchronous protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after
reset).
1: NWAIT signal is taken in to account when running an asynchronous protocol.
Bit 14 EXTMOD: Extended mode enable
This bit enables the FSMC to program the write timings for non multiplexed asynchronous accesses
inside the FSMC_BWTR register, thus resulting in different timings for read and write operations.
0: values inside FSMC_BWTR register are not taken into account (default after reset)
1: values inside FSMC_BWTR register are taken into account
Note: When the Extended mode is disabled, the FSMC can operate in mode 1 or mode 2 as follows:
– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP = 0x0 or 0x01)
– Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).
Bit 13 WAITEN: Wait enable bit
This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in
Synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed Flash latency period).
1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to
insert wait states if asserted) (default after reset).
Bit 12 WREN: Write enable bit
This bit indicates whether write operations are enabled/disabled in the bank by the FSMC.
0: Write operations are disabled in the bank by the FSMC, an AHB error is reported.
1: Write operations are enabled for the bank by the FSMC (default after reset).
Bit 11 WAITCFG: Wait timing configuration
The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be
inserted when accessing the memory in Synchronous mode. This configuration bit determines if
NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset).
1: NWAIT signal is active during wait state (not used for PSRAM).
Bit 10 Reserved, must be kept at reset value.
To Next Page
Loading...
Need help?
General
