RM0402 Rev 6 711/1163
RM0402 Fast-mode Plus Inter-integrated circuit (FMPI2C) interface
722
Bit 13 START: Start generation
This bit is set by software, and cleared by hardware after the Start followed by the address
sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can
also be cleared by software by writing ‘1’ to the ADDRCF bit in the FMPI2C_ICR register.
0: No Start generation.
1: Restart/Start generation:
If the FMPI2C is already in master mode with AUTOEND = 0, setting this bit generates a
Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer.
Otherwise setting this bit generates a START condition once the bus is free.
Note: Writing ‘0’ to this bit has no effect.
The START bit can be set even if the bus is BUSY or FMPI2C is in slave mode.
This bit has no effect when RELOAD is set.
Bit 12 HEAD10R: 10-bit address header only read direction (master receiver mode)
0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit
address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
Note: Changing this bit when the START bit is set is not allowed.
Bit 11 ADD10: 10-bit addressing mode (master mode)
0: The master operates in 7-bit addressing mode,
1: The master operates in 10-bit addressing mode
Note: Changing this bit when the START bit is set is not allowed.
Bit 10 RD_WRN: Transfer direction (master mode)
0: Master requests a write transfer.
1: Master requests a read transfer.
Note: Changing this bit when the START bit is set is not allowed.
Bits 9:0 SADD[9:0]: Slave address (master mode)
In 7-bit addressing mode (ADD10 = 0):
SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9],
SADD[8] and SADD[0] are don't care.
In 10-bit addressing mode (ADD10 = 1):
SADD[9:0] should be written with the 10-bit slave address to be sent.
Note: Changing these bits when the START bit is set is not allowed.
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