Freescale Semiconductor MPC5604B - Page 165

MPC5604B/C Microcontroller Reference Manual, Rev. 8
154 Freescale Semiconductor
8.3.1.8 RESET Mode Configuration Register (ME_RESET_MC)
This register configures system behavior during RESET mode. Please refer to Table 8-11 for details.
CDP_PRPH
_64_95
Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any peripheral
appearing in ME_PS2 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_32_63
Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any peripheral
appearing in
ME_PS1 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
CDP_PRPH
_0_31
Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any peripheral
appearing in
ME_PS0 has been requested to have its clock disabled. It is cleared when all these
peripherals which have been requested to have their clocks disabled have entered the state in which
their clocks may be disabled.
0 No peripheral clock disabling is pending
1 Clock disabling is pending for at least one peripheral
Address 0xC3FD_C020 Access: Supervisor read/write
0123456789101112131415
R
00000000PDO00
MVRON
DFLAON CFLAON
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000000000
FMPLLON
FXOSCON
FIRCON
SYSCLK
W
Reset0000000000010000
Figure 8-9. Invalid Mode Transition Status Register (ME_IMTS)
Table 8-10. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued)
Field Description