MPC5604B/C Microcontroller Reference Manual, Rev. 8
156 Freescale Semiconductor
NOTE
Byte and half-word write accesses are not allowed to this register.
8.3.1.11 DRUN Mode Configuration Register (ME_DRUN_MC)
This register configures system behavior during DRUN mode. Please refer to Table 8-11 for details.
NOTE
Byte and half-word write accesses are not allowed to this register.
NOTE
The values of FXOSCON, CFLAON and DFLAON are retained through
STANDBY mode.
Address 0xC3FD_C02C Access: Supervisor read/write
0123456789101112131415
R
00000000PDO00
MVRON
DFLAON CFLAON
W
Reset0000000000011111
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000000000
FMPLLON
FXOSCON
FIRCON
SYSCLK
W
Reset0000000000010000
Figure 8-12. DRUN Mode Configuration Register (ME_DRUN_MC)
To Next Page
Loading...
