4.49
Date Code 20170927 Instruction Manual SEL-751 Relay
Protection and Logic Functions
Group Settings (SET Command)
Note in Figure 4.36 and Figure 4.38 that the negative-sequence voltage-polar-
ized directional element has priority over the positive-sequence voltage-polar-
ized directional element in controlling the phase overcurrent elements. The
negative-sequence voltage-polarized directional element operates for unbal-
anced faults while the positive-sequence voltage-polarized directional element
operates for three-phase faults.
Note also in Figure 4.38 that the assertion of ZLOAD disables the positive-
sequence voltage-polarized directional element. ZLOAD asserts when the
relay is operating in a user-defined load region (see Figure 4.7).
Directional Element Routing
Refer to Figure 4.36 and Figure 4.39.
The directional element outputs are routed to the forward (Relay Word bits
DIRQF and DIRPF) and reverse (Relay Word bits DIRQR and DIRPR) logic
points and then on to the direction forward/reverse logic in Figure 4.40 and
Figure 4.41.
Loss-of-Potential
If EFWDLOP := Y and a loss-of-potential condition occurs (Relay Word bit
LOP asserts), then the forward logic points (Relay Word bits DIRQF and
DIRPF) assert to logical 1, thus enabling the negative-sequence and phase
overcurrent elements that are set direction forward (with settings DIR1 := F,
DIR2 := F, etc.). These direction forward overcurrent elements effectively
become nondirectional and provide overcurrent protection during a loss-of-
potential condition.
As detailed previously (in Figure 4.23 and Figure 4.38), voltage-based direc-
tional elements are disabled during a loss-of-potential condition. Thus, the
overcurrent elements controlled by these voltage-based directional elements
are also disabled. But this disable condition is overridden for the overcurrent
elements set direction forward if setting EFWDLOP := Y.
Refer to Figure 4.73 and accompanying text for more information on loss-of-
potential.
Direction Forward/Reverse Logic
Refer to Figure 4.36, Figure 4.40, and Figure 4.41.
The forward (Relay Word bits DIRQF and DIRPF) and reverse (Relay Word
bits DIRQR and DIRPR) logic points are routed to the different levels of over-
current protection by the level direction settings DIR1 through DIR4.
Table 4.25 shows the overcurrent elements that are controlled by each level
direction setting. Note in Table 4.25 that all the time-overcurrent elements
(51_T elements) are controlled by the DIR1 level direction setting.
If a level direction setting (e.g., DIR1) is set:
DIR1 = N (nondirectional)
then the corresponding Level 1 directional control outputs in Figure 4.40 and
Figure 4.41 assert to logical 1. The referenced Level 1 overcurrent elements in
Figure 4.40 and Figure 4.41 are then not controlled by the directional control
logic.
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