J.2
SEL-751 Relay Instruction Manual Date Code 20170927
MIRRORED BITS Communications
Operation
Transmitting at longer intervals for data rates faster than 9600 bps avoids
overflowing relays that receive M
IRRORED BITS at a slower rate.
Message Reception
Overview
During synchronized MIRRORED BITS communications with the
communications channel in normal state, the relay decodes and checks each
received message. If the message is valid, the relay sends each received logic
bit (RMBn, where n = 1 through 8) to the corresponding pickup and dropout
security counters, that in turn set or clear the RMBnA and RMBnB relay
element bits.
Message Decoding
and Integrity Checks
Set the RX_ID of the local SEL-751 to match the TX_ID of the remote
SEL-751. The SEL-751 provides indication of the status of each M
IRRORED
B
ITS communications channel with Relay Word bits ROKA (receive OK) and
ROKB. During normal operation, the relay sets the ROKc (c = A or B). Upon
detecting any of the following conditions, the relay clears the ROKc bit when:
➤ The relay is disabled.
➤ MIRRORED BITS communications is not enabled.
➤ Parity, framing, or overrun errors.
➤ Receive message identification error.
➤ No message received in the time three messages have been sent
when PROTO = MBc, or seven messages have been sent when
PROTO = MB8c.
➤ Loopback is enabled.
The relay asserts ROKc only after successful synchronization as in the
following description and after two consecutive messages pass all of the data
checks previously described. After ROKc is reasserted, received data may be
delayed while passing through the security counters described in the following
text.
While ROKc is deasserted, the relay does not transfer new RMB data to the
pickup-dropout security counters described in the following text. Instead, the
relay sends one of the user-definable default values to the security counter
inputs. For each RMBn, use the RXDFLT setting to determine the default state
the M
IRRORED BITS should use in place of received data if the relay detects an
error condition. The setting is a mask of 1s, 0s, and/or Xs (for RMB1A–
RMB8A), where X represents the most recently received valid value. The
positions of the 1s and 0s correspond to the respective positions of the
M
IRRORED BITS in the Relay Word bits (see Appendix K: Relay Word Bits).
Table J.2 is an extract of Appendix K: Relay Word Bits, showing the positions
of the M
IRRORED BITS.
Ta b l e J.1 N u m be r of M IRRORED BITS Messages for Different Data Rates
Rate Transmission Rate of MIRRORED BITS Packets
2400 15 ms
4800 7.5 ms
9600 4 times per power system cycle (automatic pacing mode)
19200 4 times per power system cycle (automatic pacing mode)
38400 4 times per power system cycle (automatic pacing mode)
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