4.35
Date Code 20170927 Instruction Manual SEL-751 Relay
Protection and Logic Functions
Group Settings (SET Command)
then the forward logic point (Relay Word bit DIRGF in Figure 4.32 and
DIRNF in Figure 4.33) asserts to logical 1, thus, enabling the residual ground
(Figure 4.34) and neutral ground (Figure 4.35) overcurrent elements that are
set direction forward (with settings DIR1 := F, DIR2 := F, etc.). These direc-
tion forward overcurrent elements effectively become nondirectional and pro-
vide overcurrent protection during a loss-of-potential condition.
If Global setting VSCONN := 3V0 and setting EFWDLOP := Y, the LOP con-
dition will not cause the forward directional outputs to assert when either
directional element enable DIRVE or DIRNE is asserted, as shown at the top
of Figure 4.32 and Figure 4.33. In this situation, the elements that are enabled
by signals DIRVE and DIRNE are still able to operate reliably during a loss-
of-potential condition, so there is no need to force the forward outputs to
assert. However, when DIRVE or DIRNE are not asserted, a standing LOP
condition will force the forward outputs to assert continuously. Consider this
when determining residual- and neutral-ground overcurrent element pickup
settings and time delay settings, so that “load conditions” do not cause a for-
ward-set ground directional overcurrent element to pick up and start timing.
As detailed previously in Internal Enables on page 4.31, some or all of the
voltage-based directional elements are disabled during a loss-of-potential con-
dition. Thus, the overcurrent elements controlled by these voltage-based direc-
tional elements are also disabled. However, this disable condition is
overridden for these overcurrent elements set direction forward if setting
EFWDLOP := Y.
Refer to Figure 4.73 and accompanying text for more information on loss-of-
potential.
Direction Forward/Reverse Logic
Refer to Figure 4.20, Figure 4.21, Figure 4.34, and Figure 4.35.
The forward (Relay Word bit DIRGF in Figure 4.34 and DIRNF in
Figure 4.35) and reverse (Relay Word bit DIRGR in Figure 4.34 and DIRNR
in Figure 4.35) logic points are routed to the different levels of overcurrent
protection by the level direction settings DIR1 through DIR4 and correspond-
ing GnDIR and NnDIR (n = 1–4) Relay Word bits.
Table 4.25 shows the overcurrent elements that are controlled by each level
direction setting. Note in Table 4.25 that all the time-overcurrent elements
(51_T elements) are controlled by the DIR1 level direction setting.
If a level direction setting (e.g., DIR1) is set:
DIR1 = N (nondirectional)
then the corresponding Level 1 directional control outputs in Figure 4.34 and
Figure 4.35 assert to logical 1. The referenced Level 1 overcurrent elements in
Figure 4.34 and Figure 4.35 are then not controlled by the directional control
logic.
See the beginning of Directional Control Settings on page 4.53 for a discus-
sion of the operation of level direction settings DIR1 through DIR4 when the
directional control enable setting EDIR is set to EDIR := N.
In some applications, level direction settings DIR1 through DIR4 are not flex-
ible enough in assigning the desired direction for certain overcurrent elements.
Directional Control Provided by Torque Control Settings on page 4.77
describes how to avoid this limitation for special cases.
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