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Schweitzer Engineering Laboratories SEL-751 - Table 4.59 Latch Bits Equation Settings; Figure 4.93 Schematic Diagram of a Traditional Latching Device; Figure 4.94 Logic Diagram of a Latch Switch

Schweitzer Engineering Laboratories SEL-751
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4.159
Date Code 20170927 Instruction Manual SEL-751 Relay
Protection and Logic Functions
Logic Settings (SET L Command)
Figure 4.93 Schematic Diagram of a Traditional Latching Device
Thirty-two latch control switches in the SEL-751 provide latching device
functionality. Figure 4.94 shows the logic diagram of a latch switch. The out-
put of the latch control switch is a Relay Word bit LTn (n = 01–32), called a
latch bit.
Figure 4.94 Logic Diagram of a Latch Switch
If setting SETn asserts to logical 1, latch bit LTn asserts to logical 1. If setting
RSTn asserts to logical 1, latch bit LTn deasserts to logical 0. If both settings
SETn and RSTn assert to logical 1, setting RSTn has priority and latch bit LTn
deasserts to logical 0. You can use these latch bits in SEL
OGIC control equa-
tions to create custom logic for your application.
The SEL-751 includes 32 latches. Ta ble 4.59 shows the SET and RESET
default settings for Latch 1 through Latch 4. The remaining latches are all set
to NA.
Table 4.59 Latch Bits Equation Settings
Settings Prompt Setting Range Setting Name := Factory Default
SET01 SELOGIC SET01 := NA
RST01 SEL
OGIC RST01 := NA
SET02 SEL
OGIC SET02 := R_TRIG SV02T AND NOT LT02
RST02 SEL
OGIC RST02 := R_TRIG SV02T AND LT02
SET03 SEL
OGIC SET03 := PB03_PUL AND LT02 AND NOT 52A
RST03 SEL
OGIC RST03 := (PB03_PUL OR PB04_PUL OR
SV03T) AND LT03
SET04 SEL
OGIC SET04 := PB04_PUL AND 52A
RST04 SEL
OGIC RST04 := (PB03_PUL OR PB04_PUL OR
SV04T) AND LT04
SET32 SEL
OGIC SET32 := NA
RST32 SEL
OGIC RST32 := NA
Set
Input
Reset
Input
Output
Contact
Traditional
Latching
Relay
(+)
(–)
LTn
SETn
RSTn
(Set)
(Reset)
(n = 01 through 32)
Relay
Word
Bits
SELOGIC
Setting

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