Schweitzer Engineering Laboratories SEL-751

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SET.76

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SEL-751 Settings Sheets Date________________

IEC 60870-5-103 Map Settings (SET I Command) Binary Target Map

SEL-751 Relay Instruction Manual Date Code 20170927

Binary Target Map

Fault Analog Map

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Main Page

Table of Contents3
Overview25
Communications Protocol26
- Settings30
- Overview37
Table 1.2 Current (ACI) and Voltage (AVI) Card Selection for SEL-751 Models38
Table 1.1 Phase and Neutral Current Ratings Selection for the SEL-751 Models38
Table 1.3 SEL-751 Protection Elements38
Table 1.4 SEL-751 Front-Panel Options40
Models, Options, and Accessories41
Applications43
Figure 1.1 SEL-751 Feeder Protection Relay Applied Throughout the Power System44
Figure 1.2 Typical Current Connections45
Getting Started45
Figure 1.3 Response Header46
Table 1.5 SEL-751 Serial Port Settings46
Figure 1.4 STA Command Response-No Communications Card or47
Figure 1.5 STA Command Response-Communications Card/Devicenet Protocol47
Definitions48
Specifications49
Overview57
I/O Configuration58
Figure 2.1 Relay Panel-Mount Dimensions58
Figure 2.2 Slot Allocations for Different Cards59
Table 2.1 Power Supply Inputs (PSIO/2 DI/3 DO) Card Terminal Designations60
Table 2.2 Communications Ports60
Table 2.3 Communications Card Interfaces and Connectors62
Table 2.4 Current/Voltage Inputs (4 ACI/3 AVI) Card Terminal Designations63
Table 2.5 Current Inputs (4 ACI) Card Terminal Designations63
Table 2.6 Voltage/Arc-Flash Detection Inputs (2 AVI/4 AFDI) Card Terminal Designations64
Table 2.7 Eight Arc-Flash Detection Inputs (8 AFDI) Card Terminal Designations64
Table 2.8 Eight Analog Inputs (8 AI) Card Terminal Designations65
Table 2.9 Four Analog Inputs/Four Analog Outputs (4 AI/4 AO) Card Terminal Designations65
Table 2.10 I/O (3 DI/4 DO/1 AO) Card Terminal Designations66
Table 2.11 RTD (10 RTD) Card Terminal Designations66
Table 2.12 Four Digital Inputs, One Form B Digital Output, Two Form C Digital Outputs (4 DI/3 DO) Card Terminal Designations67
Table 2.13 Four Digital Inputs/Four Digital Outputs (4 DI/4 DO) Card Terminal Designations67
Table 2.14 Eight Digital Inputs (8 DI) Card Terminal Designations68
Table 2.15 Eight Digital Outputs (8 DO) Card Terminal Designations68
Table 2.16 Fourteen Digital Inputs (14 DI) Card Terminal Designations69
Figure 2.3 Circuit Board of Analog I/O Board, Showing Jumper Selection73
Figure 2.4 JMP1 through JMP4 Locations on 4 AI/4 AO Board73
Figure 2.5 Current Output Jumpers73
Figure 2.6 Voltage Output Jumpers73
Table 2.17 Jumper Functions and Default Positions74
Relay Connections75
Figure 2.8 Dual Fiber Ethernet with 2 AVI/4 AFDI Voltage Option with Arc-Flash Detector Inputs, Devicenet Card, and Fast Hybrid 4 DI/4 DO Card (Relay MOT 751501AA3CA70850830)75
Figure 2.9 Single Copper Ethernet, EIA-485 Communication, 8 DO (Form A) Card76
Figure 2.10 Single Copper Ethernet with EIA-232 Communication, 10 RTD Card, 4 DI/4 DO Card and 2 AVI/4 AFDI Voltage Option Card with Arc-Flash Detector Inputs (Relay MOT 751501A1A9X70850230)76
Figure 2.11 no Ethernet, EIA-232 Serial Communications, EIA-232/EIA-485 Communications Card, 8 DI Card, and 8 DO Card (Form A) (Relay MOT 751401AA03A2A850000)77
Figure 2.12 Dual Copper Ethernet, 4 DI/4 DO Card, 14 DI Card, 8 AFDI with Arc-Flash Detector77
With 5 a Phase, 200 Ma Neutral, and Three-Phase LEA Voltage Inputs (8 Vac Relay MOT 751501A4A2BL0L70671)78
Figure 2.13 Dual Copper Ethernet, 14 DI Card, 8 DO (Form B) Card, 2 AVI/4 AFDI Card78
Figure 2.14 Dual 10/100 Base-T Ethernet, EIA-232 Rear Port, Without Single Multimode78
Figure 2.15 Control I/O Connections-4 AI/4 AO Option in Slot D and Fiber-Optic Port in Slot B81
Figure 2.16 Control I/O Connections-Internal RTD Option in Slot D81
AC/DC Control Connection Diagrams82
Figure 2.17 Analog Output Wiring Example82
Table 2.18 Typical Maximum RTD Lead Length82
Figure 2.18 Output OUT103 Relay Output Contact Configuration82
Figure 2.19 OUT103 Contact Fail-Safe and Nonfail-Safe Options83
Figure 2.20 Single-Phase Voltage Connections84
Figure 2.21 Voltage Connections85
Figure 2.22 Typical Current Connections87
Figure 2.23 SEL-751 Provides Overcurrent Protection and Reclosing for a Distribution Feeder (Includes Fast Bus Trip Scheme) (Delta-Connected Pts)88
Figure 2.24 SEL-751 Provides Overcurrent Protection for a Distribution Bus (Includes Fast Bus Trip Scheme) (Wye-Connected Pts)89
Figure 2.25 Transmission Line Directional Overcurrent Protection and Reclosing with Current-Polarization Source Connected to Channel in (Wye-Connected Pts)90
Figure 2.26 SEL-751 Provides Overcurrent Protection for a Delta-Wye Transformer Bank (Wye-Connected Pts)91
Figure 2.27 SEL-751 Provides Overcurrent Protection for a Transformer Bank with a Tertiary Winding (Wye-Connected Pts)92
Figure 2.28 SEL-751 Provides Overcurrent Protection for an Industrial Distribution Feeder (Core-Balance Current Transformer Connected to Channel IN)93
Figure 2.29 SEL-751 Provides Overcurrent Protection for a High-Impedance or Low-Impedance Grounded System (Wye-Connected Pts)94
Figure 2.30 SEL-751 Provides Overcurrent Protection for a Petersen Coil-Grounded System (Wye-Connected Pts)95
Figure 2.31 SEL-751 Provides Overcurrent Protection for an Ungrounded System (Wye-Connected Pts)96
Figure 2.32 SEL-751 Provides Overcurrent Protection for an Ungrounded System (Open-Delta Connected Pts, Broken-Delta 3V0 Connection)97
Figure 2.33 SEL-751 with a 2 AVI/4 AFDI Option Card and the Fiber-Optic-Based Point-Sensor98
Arc-Flash Protection: System Installation98
Figure 2.34 Black-Jacketed Fiber Installation Example99
Figure 2.35 Point-Sensor Assembly99
Figure 2.36 Point-Sensor Installation99
Figure 2.37 Point-Sensor Directivity (0-360° Around the Mounting Plane)100
Figure 2.38 Point-Sensor Directivity (Front to Back, above the Mounting Plane)100
Figure 2.39 Point-Sensor Directivity (Left to Right, above the Mounting Plane)101
Figure 2.40 Clear-Jacketed Fiber Sensor Assembly101
Figure 2.41 Clear-Jacketed Fiber Sensor Mounting Example102
Figure 2.42 Clear-Jacketed Fiber Sensor Components (V-Pin Style)102
Figure 2.43 Clear-Jacketed Fiber Sensor Showing Transition from Clear- to Black-Jacketed Fiber Section102
Figure 2.44 Switchgear Application Example103
Figure 2.45 Bare-Fiber Sensor Assembly with Two Splices104
Figure 2.46 Point Sensor Assembly104
Table 2.19 Optical Budget Calculations104
Figure 2.47 Bare-Fiber Sensor Assembly with Two Additional ST Splice Connectors105
Field Serviceability106
Figure 2.48 Point Sensor Assembly with Two V-Pin Splice Connectors106
Overview109
Table 3.1 SEL Software Solutions109
Setup110
Figure 3.1 Serial Port Communications Dialog Box110
Table 3.2 AC SEL ERATOR Quickset SEL-5030 Software110
Terminal111
Figure 3.3 Network Communication Parameters Dialog Box111
Figure 3.4 Communications Menu111
Settings Database Management and Drivers112
Figure 3.5 Device Response to the ID Command112
Settings114
Table 3.3 File/Tools Menus115
Figure 3.6 Selection of Drivers115
Figure 3.7 Update Part Number116
Figure 3.8 New Setting Screen116
Figure 3.9 Expressions Created with Expression Builder118
Event Analysis119
Figure 3.10 Composite Screens for Retrieving Events119
Figure 3.11 Saving the Retrieved Event120
Meter and Control121
Figure 3.12 Device Overview Screen121
Figure 3.13 Control Screen122
Figure 3.14 Remote Operation Selection123
Figure 3.15 Language Support Options123
Figure 3.16 Spanish Settings Quickset Display124
Figure 3.17 Spanish Control Window (Ventana de Control) Display125
Table 3.4 Quickset Help126
Overview127
Application Data129
Table 4.1 Identifier Settings129
Table 4.2 CT Configuration Settings130
Table 4.3 Voltage Configuration Settings130
Table 4.4 Effect on Group Settings When SINGLEV := y131
Table 4.5 Main Relay Functions that Change with VNOM := off133
Figure 4.1 Low-Energy Analog Voltage Sensor (Capacitive Voltage Divider)133
Table 4.6 Line Parameter Settings136
Table 4.7 Fault Locator Setting137
Table 4.8 Maximum Phase Overcurrent Settings138
Table 4.9 Neutral Overcurrent Settings139
Figure 4.2 Instantaneous Overcurrent Element Logic140
Table 4.10 Residual Overcurrent Settings141
Table 4.11 Negative-Sequence Overcurrent Settings141
Figure 4.3 Instantaneous Overcurrent Element Pickup Time Curve142
Figure 4.4 Instantaneous Overcurrent Element Reset Time Curve142
Table 4.12 A-, B-, and C-Phase Time-Overcurrent Settings143
Table 4.13 Maximum Phase Time-Overcurrent144
Figure 4.5 Phase Time-Overcurrent Elements 51AT, 51BT, and 51CT144
Table 4.14 Negative-Sequence Time-Overcurrent Settings145
Figure 4.6 Maximum Phase Time-Overcurrent Elements 51P1T and 51P2T145
Table 4.15 Neutral Time-Overcurrent Settings146
Figure 4.7 Negative-Sequence Time-Overcurrent Element 51QT146
Table 4.16 Residual Time-Overcurrent Settings147
Figure 4.8 Neutral Time-Overcurrent Elements 51N1T and 51N2T147
Figure 4.9 Residual Time-Overcurrent Elements 51G1T and 51G2T148
Table 4.17 Equations Associated with U.S. Curves149
Table 4.18 Equations Associated with IEC Curves149
Figure 4.13 U.S. Extremely Inverse Curve: U4150
Figure 4.10 U.S. Moderately Inverse Curve: U1150
Figure 4.11 U.S. Inverse Curve: U2150
Figure 4.12 U.S. very Inverse Curve: U3150
Figure 4.14 U.S. Short-Time Inverse Curve: U5151
Figure 4.15 IEC Class a Curve (Standard Inverse): C1151
Figure 4.16 IEC Class B Curve (very Inverse): C2151
Figure 4.17 IEC Class C Curve (Extremely Inverse): C3151
Figure 4.18 IEC Long-Time Inverse Curve: C4152
Figure 4.19 IEC Short-Time Inverse Curve: C5152
Figure 4.21 General Logic Flow of Directional Control for Neutral Ground and Residual Ground Overcurrent Elements (Ungrounded/High-Impedance Grounded Systems; ORDER := U)154
Table 4.19 Available Ground Directional Elements154
Table 4.20 Best Choice Ground Directional Element Logic155
Table 4.21 Ground Directional Element Availability by Voltage Connection Settings156
Table157
- Figure 4.22 Logic for Relay Word Bit GNDSW158
- Table159
- Table160
- Table161
- Table162
Figure 4.23 Internal Enables (DIRQE and DIRQGE) Logic for Negative-Sequence Voltage-Polarized Directional Elements162
Table163
Figure 4.24 Internal Enables (DIRVE and DIRIE) Logic for Zero-Sequence Voltage-Polarized and Channel in Current-Polarized Directional Elements163
Table164
Figure 4.25 Internal Enable (DIRNE) Logic for Zero-Sequence Voltage-Polarized Directional Elements (Low-Impedance Grounded, Petersen Coil-Grounded, and Ungrounded/High-Impedance Grounded Systems)164
Table165
Figure 4.26 Negative-Sequence Voltage-Polarized Directional Element for Neutral Ground and Residual Ground Overcurrent Elements165
Table166
Figure 4.27 Zero-Sequence Voltage-Polarized Directional Element166
Figure 4.28 Channel in Current-Polarized Directional Element167
Figure 4.29 Zero-Sequence Voltage-Polarized Directional Element (Low-Impedance Grounded Systems)168
Figure 4.30 Wattmetric and Incremental Conductance Directional Elements (Petersen Coil-Grounded Systems)169
Figure 4.31 Zero-Sequence Voltage-Polarized Directional Element (Ungrounded/High-Impedance Grounded Systems)170
Figure 4.32 Routing of Directional Elements to Residual Ground Overcurrent Elements171
Figure 4.33 Routing of Directional Elements to Neutral Ground Overcurrent Elements171
Figure 4.34 Direction Forward/Reverse Logic for Residual Ground Overcurrent Elements172
Figure 4.35 Direction Forward/Reverse Logic for Neutral Ground Overcurrent Elements173
Figure 4.36 General Logic Flow of Directional Control for Negative-Sequence and Phase Overcurrent Elements174
Figure 4.37 Negative-Sequence Voltage-Polarized Directional Element for Negative-Sequence and Phase Overcurrent Elements176
Figure 4.38 Positive-Sequence Voltage-Polarized Directional Element for Phase Overcurrent Elements177
Figure 4.39 Routing of Directional Elements to Negative-Sequence and Phase Overcurrent Elements178
Figure 4.40 Direction Forward/Reverse Logic for Negative-Sequence Overcurrent Elements178
Figure 4.41 Direction Forward/Reverse Logic for Phase Overcurrent Elements179
Table 4.22 Directional Control Settings179
Table 4.23 Wattmetric Settings180
Table181
- Table 4.24 Directional Control Settings Not Made for Particular Conditions182
- Table 4.25 Overcurrent Elements Controlled by Level Direction Settings DIR1 through DIR4 (Corresponding Overcurrent Element Figure Numbers in Parentheses)182
- Table184
- Table185
Figure 4.44 Zero-Sequence Impedance Network and Relay Polarity190
Figure 4.45 Zero-Sequence Impedance Plot for Solidly-Grounded, Mostly Inductive System190
Figure 4.46 Low-Impedance Grounded Distribution System with a Ground Fault on Feeder191
Figure 4.47 Zero-Sequence Impedance Network for Low-Impedance Grounded Distribution System with a Ground Fault on Feeder192
Figure 4.50 Zero-Sequence Impedance Plots for Ground Fault on Low-Impedance Grounded Distribution System194
Figure 4.51 Z0MTA Setting Provides Forward/Reverse Ground Fault Discrimination in a Low-Impedance Grounded Distribution System195
Figure 4.52 Zero-Sequence Impedance Network for Ground Fault on Feeder 1198
Figure 4.53 Wattmetric Element Operation for Ground Fault on Feeder 1199
Table200
Table 4.26 Effect of Settings VSCONN and DELTA_Y on Petersen Coil Directional Elements202
Table 4.27 Load-Encroachment Settings204
Figure 4.54 Load-Encroachment Logic205
Table207
Figure 4.55 High-Impedance Fault Current Levels Depend on Ground Surface Type207
Table209
Figure 4.56 HIF Detection Block Diagram209
Table 4.28 High-Impedance Fault (HIF) Detection Settings210
Table 4.29 HIF Relay Word Bits211
Figure 4.57 A-Phase Second Harmonic Blocking212
Table 4.30 Second-Harmonic Blocking Settings213
Figure 4.58 Three-Phase Second- and Fifth-Harmonic Blocking Logic213
Table 4.31 RTD Settings215
Table 4.32 RTD Resistance Versus Temperature216
Figure 4.59 Thermal Alarm and Trip Logic220
Figure 4.60 Thermal Element Current Overload Logic220
Table 4.33 IEC Thermal Element Settings222
Table 4.34 Undervoltage Function223
Table 4.35 Overvoltage Function224
Figure 4.61 Undervoltage Element Logic225
Figure 4.62 Overvoltage Element Logic226
Table 4.36 Operating Quantities for the 27I Element227
Figure 4.63 Logic Diagram of the Inverse-Time Undervoltage Element227
Table 4.37 Inverse-Time Undervoltage Settings228
Table 4.38 Specification of Inverse-Time Undervoltage Protection Element228
Figure 4.64 Inverse Time-Undervoltage Element Curves229
Table 4.39 Operating Quantities for the 59I Element229
Figure 4.65 Logic Diagram of the Inverse-Time Overvoltage Element230
Table 4.40 Inverse-Time Overvoltage Settings230
Figure 4.66 Inverse Time-Overvoltage Element Curves231
Table 4.41 Specification of Inverse-Time Overvoltage Protection Element231
Figure 4.67 Synchronism-Check Voltage Window and Slip Frequency Elements232
Figure 4.68 Synchronism-Check Elements233
Table 4.42 Synchronism-Check Settings234
Figure 4.69 Angle Difference between VP and VS Compensated by Breaker Close Time (Fp < Fs and VP Shown as Reference in this Example)238
Table 4.43 Voltages When Setting SINGLEV := y241
Table 4.44 Power Element Settings241
Figure 4.70 Three-Phase Power Elements Logic242
Figure 4.71 Power Elements Operation in the Real/Reactive Power Plane243
Table 4.45 Power Factor Settings243
Figure 4.72 Power Factor Elements Logic244
Table 4.46 Loss-Of-Potential (LOP) Setting245
Figure 4.73 Loss-Of-Potential (LOP) Logic246
Figure 4.74 Logic Diagram of the Vector Shift Element247
Table 4.47 Vector Shift Element Settings249
Table 4.48 Frequency Settings249
Figure 4.75 Over- and Underfrequency Element Logic250
Table 4.49 Rate-Of-Change-Of-Frequency Settings250
Figure 4.76 81R Frequency Rate-Of-Change Scheme Logic251
Table 4.50 Time Window Versus 81Rntp Setting251
Figure 4.77 81RF Characteristics252
Table 4.51 Fast Rate-Of-Change-Of-Frequency Settings253
Figure 4.78 81RF Fast Rate-Of-Change-Of-Frequency Logic254
Table 4.52 Trip/Close Logic Settings255
Figure 4.79 Trip Logic255
Figure 4.81 Reclose Supervision Logic (Following Open Interval Time-Out)258
Figure 4.82 Reclose Supervision Limit Timer Operation259
Figure 4.83 SEL-751 Relays Installed at both Ends of a Transmission Line in a High-Speed Reclose Scheme262
Figure 4.84 Reclosing Relay States and General Operation264
Table 4.53 Relay Word Bit and Front-Panel Correspondence to Reclosing Relay States265
Table 4.54 Reclosing Control Settings267
Figure 4.85 Reclosing Sequence from Reset to Lockout with Example Settings268
Table 4.55 Shot Counter Correspondence to Relay Word Bits and Open Interval Times270
Table 4.56 Open Interval Time Example Settings274
Figure 4.86 Reclose Blocking for Islanded Generator274
Figure 4.87 Sequence Coordination between the SEL-751 and a Line Recloser277
Figure 4.88 Operation of SEL-751 Shot Counter for Sequence Coordination with Line Recloser (Additional Settings Example 1)277
Table 4.57 Demand Meter Settings280
Figure 4.90 Demand Current Logic Outputs280
Figure 4.91 Response of Thermal and Rolling Demand Meters to a Step Input (Setting DMTC = 15 Minutes)281
Figure 4.92 Voltage VS Applied to Series RC Circuit282
Logic Settings (SET L Command)284
Table 4.58 Enable Settings284
Table 4.59 Latch Bits Equation Settings285
Figure 4.93 Schematic Diagram of a Traditional Latching Device285
Figure 4.94 Logic Diagram of a Latch Switch285
Figure 4.96 Result of Falling-Edge Operator on a Deasserting Input290
Table 4.62 SEL OGIC Variable Settings291
Table 4.63 Counter Input/Output Description292
Table 4.64 Order of Precedence of the Control Inputs293
Figure 4.99 Example of the Effects of the Input Precedence293
Table 4.65 Control Output Equations and Contact Behavior Settings294
Table 4.66 General Global Settings295
Figure 4.100 Phase Rotation Setting295
Table 4.67 Event Messenger Settings296
Table 4.68 Setting Group Selection297
Table 4.69 LEA Ratio and Phase Correction Settings for Phase Voltages297
Table 4.70 LEA Ratio and Phase Correction Settings for Synchronism-Check Voltage298
Table 4.71 Time and Date Management Settings298
Table 4.72 Breaker Failure Setting300
Figure 4.101 Breaker Failure Logic301
Figure 4.102 Arc-Flash Instantaneous Overcurrent Element Logic302
Table 4.73 Arc-Flash Overcurrent Settings302
Table 4.74 Arc-Flash Time-Overlight Settings303
Figure 4.103 Inverse Time-Overlight Element Logic304
Figure 4.104 TOL Element Inverse Curve Characteristic304
Table 4.75 Typical Ambient Illumination Light Levels305
Figure 4.105 Analog Input Card Adaptive Name306
Table 4.76 Summary of Steps307
Figure 4.106 Settings to Configure Input 1 as a 4-20 Ma Transducer Measuring Temperatures between -50°C and 150°C309
Table 4.77 Analog Input Card Settings in Slot309
Figure 4.107 Analog Output Number Allocation310
Table 4.78 Analog Output Card Settings in Slot 3310
Figure 4.108 Analog Output Settings311
Figure 4.109 DC Mode Processing312
Figure 4.110 AC Mode Processing312
Figure 4.111 Timing Diagram for Debounce Timer Operation When Operating in AC Mode312
Table 4.81 Setting Change Disable Setting313
Table 4.79 Slot C Input Debounce Settings313
Table 4.80 Data Reset Settings313
Table 4.82 Time Synchronization Source Setting314
Table 4.83 Front-Panel Serial Port Settings314
Table 4.84 Ethernet Port Settings315
Table 4.85 Port Number Settings that Must be Unique316
Table 4.86 Fiber-Optic Serial Port Settings317
Table 4.87 Rear-Panel Serial Port (EIA-232) Settings317
Table 4.88 Rear-Panel Serial Port (EIA-232/EIA-485) Settings318
Table 4.89 Rear-Panel Devicenet Port Settings319
Front-Panel Settings (SET F Command)319
Table 4.90 Display Point and Local Bit Default Settings320
Table 4.91 LCD Display Settings320
Table 4.92 Settings that Always, Never, or Conditionally Hide a Display Point322
Table 4.93 Entries for the Four Strings322
Figure 4.112 Display Point Settings323
Figure 4.113 Front-Panel Display-Both HV and LV Breakers Open323
Figure 4.114 Front-Panel Display-HV Breaker Closed, LV Breaker Open323
Figure 4.115 Front-Panel Display-Both HV and LV Breakers Closed324
Table 4.94 Binary Entry in the Name String Only324
Figure 4.116 Front-Panel Display-HV Breaker Open, LV Breaker Closed324
Figure 4.117 Front-Panel Display-HV Breaker Open, LV Breaker Closed324
Figure 4.118 Front-Panel Display for a Binary Entry in the Name String Only324
Table 4.95 Analog Entry in the Name String Only325
Figure 4.119 Front-Panel Display for an Analog Entry in the Name String Only325
Table 4.97 Example Settings and Displays326
Table 4.96 Entry in the Name String and the Alias Strings326
Figure 4.120 Front-Panel Display for an Entry in (A) Boolean Name and Alias Strings and (B) Analog Name and User Text and Formatting Strings326
Figure 4.121 Front-Panel Display for an Entry in (A) Boolean Name and Alias Strings and (B) Analog Name, User Text and Formatting Strings, and Engineering Units326
Figure 4.122 Adding Temperature Measurement Display Points327
Figure 4.123 Rotating Display327
Figure 4.124 Adding Two Local Bits328
Table 4.98 Target LED Settings329
Table 4.99 Pushbutton LED Settings330
Report Settings (SET R Command)331
Table 4.100 Auto-Removal Settings332
Table 4.101 SER Trigger Settings332
Table 4.102 Enable Alias Settings332
Table 4.103 SET R SER Alias Settings333
Table 4.104 Event Report Settings333
Table 4.105 HIF Event Report Settings334
Table 4.106 Load Profile Settings334
Table 4.107 DNP Map Settings334
Modbus Map Settings (SET M Command)335
Table 4.108 User Map Register Settings335
Overview337
Figure 5.1 Complex Power Measurement Conventions338
Table 5.1 Measured Fundamental Meter Values339
Table 5.2 Thermal Meter Values341
Figure 5.3 METER T Command Report with Rtds342
Table 5.3 RTD Input Status Messages342
Figure 5.4 METER E Command Response343
Figure 5.5 METER RE Command Response343
Table 5.4 Maximum/Minimum Meter Values343
Figure 5.6 METER M Command Response344
Figure 5.7 METER RM Command Response344
Figure 5.8 METER MV Command Response345
Figure 5.9 METER RMS Command Response345
Table 5.5 RMS Meter Values345
Figure 5.10 METER AI Command Response346
Figure 5.11 METER L (Light) Command Response346
Figure 5.12 MET de Command Response347
Table 5.6 Demand Values347
Figure 5.13 MET PE Command Response347
Table 5.7 Synchrophasor Measured Values348
Figure 5.14 MET RA Command Response349
Table 5.8 High-Impedance Fault Metering Measured Values349
Figure 5.15 MET H (HIF) Command Response349
Load Profiling350
Table 5.9 Station DC Battery Monitor Settings351
Figure 5.16 LDP Command Response351
Figure 5.17 DC Under- and Overvoltage Elements352
Breaker Monitor355
Table 5.10 Breaker Maintenance Information for a 25 Kv Circuit Breaker355
Table 5.11 Breaker Monitor Settings356
Figure 5.19 Plotted Breaker Maintenance Points for a 25 Kv Circuit Breaker357
Figure 5.20 SEL-751 Breaker Maintenance Curve for a 25 Kv Circuit Breaker358
Figure 5.22 Breaker Monitor Accumulates 10 Percent Wear360
Figure 5.23 Breaker Monitor Accumulates 25 Percent Wear361
Figure 5.24 Breaker Monitor Accumulates 50 Percent Wear362
Figure 5.25 Breaker Monitor Accumulates 100 Percent Wear363
Figure 5.26 Input Inxxx Connected to Trip Bus for Breaker Monitor Initiation365
Overview367
Table 6.1 Methods of Accessing Settings367
View/Change Settings with the Two-Line Front Panel368
Figure 6.1 Front-Panel Setting Entry Example369
View/Change Settings with the Touchscreen Front Panel370
Table 6.2 SHOW Command Options370
Table 6.3 SET Command Options370
Table 6.4 SET Command Editing Keystrokes371
Setting Entry Error Messages372
- Table SET.1 Range Dependencies for the EDIR Setting378
- Table SET.2 Range Dependencies for the ORDER Setting378
- Table SET.3 Range Dependencies for 27I Operating Quantities385
- Table SET.4 Range Dependencies for 59I Operating Quantities386
- Table SET.5 Port Number Settings that Must be Unique423
Table 6.5 SET Command Format372
Appendix G: IEC 60870-5-103 Communications451
Overview451
Table 7.1 SEL-751 Communications Port Interfaces451
Figure 7.1 Simple Ethernet Network Configuration453
Figure 7.2 Ethernet Network Configuration with Dual Redundant Connections (Failover Mode)454
Figure 7.3 Ethernet Network Configuration with Ring Structure (Switched Mode)454
Figure 7.4 IRIG-B Input (Relay Terminals B01-B02)456
Table 7.2 PRP Settings456
Figure 7.5 IRIG-B Input Via EIA-232 Port 3 (SEL Communications Processor as Source)457
Figure 7.6 IRIG-B Input Via EIA-232 Port 3 (SEL-2401/2404/2407 Time Source)457
Figure 7.7 IRIG-B Input Via Fiber-Optic EIA-232 Port 2 (SEL-2030/2032 Time Source)457
Figure 7.8 IRIG-B Input Via Fiber-Optic EIA-232 Port 2 (SEL-2401/2404/2407 Time Source)458
Figure 7.9 EIA-232 DB-9 Connector Pin Numbers458
Table 7.3 EIA-232/EIA-485 Serial Port Pin Functions458
Table459
Figure 7.10 SEL Cable C234A-SEL-751 to DTE Device459
Figure 7.11 SEL Cable C227A-SEL-751 to DTE Device459
Figure 7.12 SEL Cable C222-SEL-751 to Modem460
Figure 7.13 SEL Cable C272A-SEL-751 to SEL Communications Processor Without IRIG-B Signal460
Figure 7.14 SEL Cable C273A-SEL-751 to SEL Communications Processor with IRIG-B Signal460
Figure 7.15 SEL Cable C387-SEL-751 to SEL-3010460
Communications Protocols461
Table 7.4 Protocols Supported on the Various Ports461
Table 7.5 Settings Associated with SNTP465
Figure466
Table 7.6 Serial Port Automatic Messages467
Table 7.7 Command Response Header Definitions469
Table 7.8 Access Commands470
Table472
Figure 7.16 AFT Command Response472
Table 7.9 ANALOG Command473
Figure 7.17 Breaker Monitor Report474
Figure 7.18 Breaker Wear Report475
Figure 7.19 Breaker Reset Response475
Figure 7.20 CEV HIF Command Response476
Table477
Table 7.10 COM Command478
Table 7.11 CONTROL Command478
Table 7.12 Three Remote Bit States479
Table 7.13 COPY Command479
Table 7.14 COUNTER Command479
Table 7.15 Date Command479
Figure 7.21 Ethernet Port (PORT 1) Status Report When NETMODE := PRP480
Figure 7.22 Ethernet Port (PORT 1) Status Report When NETMODE := FIXED480
Figure 7.23 Ethernet Port (PORT 1) Status Report When NETMODE := FAILOVER, E61850 := Y, and EGSE := y481
Figure 7.24 Ethernet Port (PORT 1) Status Report When NETMODE := SWITCHED481
Table 7.16 EVENT Command (Event Reports)482
Table 7.17 FILE Command482
Figure 7.25 Ethernet Port (PORT 1) Status Report for the Single Ethernet Port Option482
Table 7.18 GOOSE Command Variants483
Figure 7.26 GOOSE Command Response485
Table 7.19 GROUP Command486
Table 7.21 HISTORY Command487
Table 7.22 HIS HIF Command487
Table 7.23 HSG Command488
Figure 7.27 HSG Command Response488
Table 7.24 IDENTIFICATION Command489
Table 7.25 INI HIF Command489
Table 7.26 IRI Command489
Table 7.27 LDP Commands490
Table 7.28 L_D Command (Load Firmware)490
Table 7.29 LOG HIF Command491
Figure 7.28 LOG H (HIF) Command Response491
Table 7.31 Meter Command492
Table 7.32 Meter Class493
Table 7.33 PASSWORD Command494
Table 7.34 Factory-Default Passwords for Access Levels 1, 2, and C494
Table 7.35 Valid Password Characters494
Figure 7.29 PING Command Response495
Table 7.36 PUL Outnnn Command496
Table 7.37 QUIT Command496
Table 7.38 R_S Command (Restore Factory-Defaults)496
Table 7.39 SER Command (Sequential Events Recorder Report)497
Table 7.40 SER D Command497
Table 7.41 SET Command (Change Settings)498
Table 7.42 SET Command Editing Keystrokes498
Figure 7.30 SHOW Command Example499
Table 7.43 SHOW Command (Show/View Settings)499
Table 7.44 STATUS Command (Relay Self-Test Status)501
Table 7.45 STATUS Command Report and Definitions501
Figure 7.31 Typical Relay Output for STATUS S Command502
Table 7.47 SUM HIF Command503
Table 7.48 TARGET Command (Display Relay Word Bit Status)503
Table 7.49 Front-Panel Leds and the TAR 0 Command504
Table 7.50 TEST DB Commands504
Figure 7.32 the Command Example506
Table 7.51 the Command (Preload or Reset Thermal Capacity)506
Table 7.52 TIME Command (View/Change Time)506
Table 7.53 TRIGGER Command (Trigger Event Report)507
Table 7.54 TRIGGER HIF Command507
Table 7.55 VEC Command507
Figure 7.33 CFG.TXT File508
Table 7.56 FTP and MMS Virtual File Structure508
Table 7.57 Settings Directory Files510
Table 7.58 Reports Directory Files510
Table 7.59 Event Directory Files511
Table 7.60 Files Available for Ymodem Protocol512
Table 7.61 FTP and MMS Wildcard Usage Examples513
Table 7.62 Ymodem Wildcard Usage Examples513
Appendix H: Devicenet Communications515
Overview515
Figure 8.1 SEL-751 Front-Panel Models515
Two-Line Display Front Panel516
Figure 8.2 Front-Panel Overview516
Table 8.1 Front-Panel Automatic Messages (FP_AUTO := OVERRIDE)517
Figure 8.3 Access Level Security Padlock Symbol518
Figure 8.4 Password Entry Screen518
Figure 8.5 Front-Panel Pushbuttons519
Table 8.2 Front-Panel Pushbutton Functions519
Figure 8.6 Main Menu520
Figure 8.7 MAIN Menu and METER Submenu520
Figure 8.8 METER Menu and ENERGY Submenu520
Figure 8.9 Relay Response When Energy (or Max/Min, Demand, Peak Demand) Metering Is Reset521
Figure 8.10 Relay Response When no Analog Cards Are Installed521
Figure 8.11 Relay Response When no Math Variables Enabled521
Figure 8.12 MAIN Menu and EVENTS Submenu521
Figure 8.13 EVENTS Menu and DISPLAY Submenu522
Figure 8.14 Relay Response When no Event Data Available522
Figure 8.15 Relay Response When Events Are Cleared522
Figure 8.16 MAIN Menu and TARGETS Submenu522
Figure 8.17 TARGETS Menu Navigation523
Figure 8.18 MAIN Menu and CONTROL Submenu523
Figure 8.19 CONTROL Menu and OUTPUTS Submenu524
Figure 8.20 CONTROL Menu and LOCAL BITS Submenu524
Figure 8.21 MAIN Menu and SET/SHOW Submenu525
Figure 8.22 SET/SHOW Menu526
Figure 8.23 MAIN Menu and Status Submenu526
Figure 8.24 MAIN Menu and Breaker Submenu527
Figure 8.25 Factory Default Front-Panel Leds527
Table 8.3 Possible Warning Conditions (Flashing TRIP LED)528
Figure 8.27 Operator Control Pushbuttons and Leds529
Figure 8.26 Target Reset Pushbutton529
Table 8.4 SEL-751 Front-Panel Operator Control Functions530
Figure 8.28 Touchscreen Display Components and Indicators532
Touchscreen Display Front Panel532
Table 8.5 Touchscreen Display Component and Indicator Descriptions533
Table 8.6 Front-Panel Automatic Messages534
Table 8.7 Sidebar Buttons535
Figure 8.29 Home (Default FPHOME Setting)535
Table 8.8 Home Folders and Applications536
Figure 8.30 Bay Screens Application536
Figure 8.31 Meter Applications537
Table 8.9 Meter Application Availability537
Figure 8.32 Meter Phasors538
Figure 8.33 Meter Fundamental538
Figure 8.34 Meter Energy538
Figure 8.35 Meter Energy Reset538
Table 8.10 Monitor Application Availability539
Figure 8.36 Monitor Applications539
Figure 8.37 Breaker Wear Trips539
Figure 8.38 Breaker Wear A, B, C, and Last Reset539
Table 8.11 Reports Application Availability540
Figure 8.39 Monitor Relay Word Bits540
Figure 8.40 Search Relay Word Bits540
Figure 8.41 Reports Applications540
Figure 8.44 Sequential Events Recorder541
Figure 8.45 Control Applications541
Table 8.12 Control Application Availability542
Figure 8.46 Local Bits Confirmation542
Figure 8.47 Digital Output Pulsing-Slot a542
Figure 8.48 Digital Output Pulsing Confirmation542
Figure 8.49 Local Bits543
Figure 8.50 Local Bits Notification543
Figure 8.51 Local Bits Confirmation543
Figure 8.52 Device Info Applications543
Table 8.13 Device Info Application Availability544
Figure 8.53 Device Status544
Figure 8.54 Device Configuration544
Figure 8.55 Model Number Confirmation544
Figure 8.56 Trip and Diagnostic Messages545
Figure 8.57 Arc-Flash Diagnostics545
Figure 8.58 Arc-Flash Diagnostics Confirmation545
Figure 8.59 Access Level Applications545
Table 8.14 Access Level Application Availability546
Figure 8.60 Authentication546
Figure 8.61 Login Confirmation546
Figure 8.62 Settings Folders and Applications546
Table 8.15 Settings Folder and Application Availability547
Table 8.16 Settings Folders Port, Group, and Date and Time Application Availability547
Figure 8.63 Port Settings548
Figure 8.64 Group Settings548
Figure 8.65 Set 1 Settings548
Figure 8.66 Max Phase Overcurrent Settings548
Figure 8.67 Set/Show Settings Edit548
Figure 8.68 Touchscreen Settings549
Figure 8.69 Touchscreen Settings Edit549
Figure 8.70 Rotating Display549
Appendix D: DNP3 Communications559
Overview559
Figure560
Table 9.1 Circuit Breaker Symbols560
Table 9.2 Disconnect Settings561
Table 9.3 Two-Position Disconnect Symbols561
Figure 9.1 Dual-Point Disconnect Status Logic561
Table 9.4 Local/Remote Breaker Control Settings562
Figure 9.2 Local/Remote Control Mode Indication562
Figure 9.3 Bay Screens Application Display with a Single-Line Diagram563
Figure 9.4 Breaker Control Application563
Figure 9.5 Quickset Front-Panel Options564
Table 9.5 Touchscreen Settings565
Figure 9.6 Quickset Touchscreen Settings565
Figure567
Figure 9.7 Layout of Bay Screen Builder568
Figure 9.8 Project Analysis Pane: Analysis Results Tab570
Figure 9.9 Project Analysis Pane: Constraints Summary Tab570
Figure 9.10 Bay Control Single-Line Diagram Schematic571
Figure 9.11 Device Part Number Touchscreen Configuration Option572
Figure 9.12 Quickset Bay Control Project Management and Project Preview Display572
Figure 9.13 Open Single-Line Diagram in Bay Screen Builder573
Figure 9.14 Drag-And-Drop Symbols573
Table 9.6 Symbols Required for the Single-Line Diagram Schematic in Figure574
Figure 9.15 Selected Breaker Symbol Settings Displayed in the Properties Pane575
Figure 9.16 Close/Open/Alarm Color Property Drop down Menu575
Figure 9.17 Publish Bay Screen Builder Project to Quickset576
Figure 9.18 Quickset Updated Single-Line Diagram and Corresponding Settings576
Figure578
Figure 9.19 Final Bay Screen Builder Rendering580
Figure 9.20 Import/Export of the Bay Control Screen in Quickset581
Figure 9.21 Main Bus and Transfer Bus Bay Control Single-Line Diagram581
Figure 9.22 Tie Breaker Bay Control Single-Line Diagram582
Figure 9.23 Bus 1 and Bus 2 Bay Control Single-Line Diagram582
Figure 9.24 Feeder Bay Control Single-Line Diagram582
Figure 9.25 Incomer with Step-Down Transformer Bay Control Single-Line Diagram582
Appendix E: Modbus RTU Communications583
Overview583
Event Reporting584
Figure 10.1 Example Event Summary585
Table 10.1 Event Types586
Table 10.2 Phase Involvement Event Type587
Figure 10.2 Sample Event History590
Table 10.3 Event Report Current and Voltage Columns591
Table 10.4 Output, Input, Protection, and Control Element Event Report Columns592
Figure 10.3 Example Standard 15-Cycle Event Report 1/4-Cycle Resolution594
Figure 10.4 Derivation of Event Report Current Values and RMS Current Values from Sampled Current Waveform599
Figure 10.5 Derivation of Phasor RMS Current Values from Event Report Current Values600
Figure 10.6 Sample Compressed ASCII Event Report601
Figure 10.7 Sample CEV Report Viewed with Analytic Assistant or605
Figure 10.8 Options for Converting CEV Reports to COMTRADE in Analytic Assistant606
Figure 10.9 Sample COMTRADE .HDR Header File607
Figure 10.10 Sample COMTRADE .CFG Configuration File Data610
High-Impedance Fault (HIF) Event Reporting611
Figure 10.11 Sample HIF Event Summary Report612
Table 10.5 CEV HIF Commands612
Table 10.6 HIF Event Types613
Table 10.7 HIF Event Phases613
Table 10.8 HIF Downed Conductor614
Table 10.9 SUM HIF Command614
Figure 10.12 Sample Compressed ASCII HIF Summary615
Figure 10.13 Sample HIF Event History615
Figure 10.14 Sample Compressed HIF History Report616
Table 10.10 HIS HIF Command616
Figure 10.15 Sample HIF COMTRADE .HDR Header File617
Figure 10.16 Sample HIF COMTRADE .CFG Configuration File Data617
Figure 10.17 Example Sequential Events Recorder (SER) Event Report619
Overview621
Table 11.1 Resultant Scale Factors for Inputs622
Figure 11.1 Low-Level Test Interface (J2 and J4)622
Commissioning Tests623
Figure 11.2 Three-Phase Wye AC Connections625
Figure 11.3 Three-Phase Open-Delta AC Connections625
Table 11.2 Serial Port Commands that Clear Relay Data Buffers626
Table 11.3 Phase Current Measuring Accuracy627
Figure 11.4 Current Source Connections627
Table 11.4 Current Unbalance Measuring Accuracy628
Figure 11.5 Wye Voltage Source Connections628
Table 11.5 Power Quantity Accuracy-Wye Voltages629
Figure 11.6 Delta Voltage Source Connections629
Table 11.6 Power Quantity Accuracy-Delta Voltages630
Periodic Tests (Routine Maintenance)632
Figure 11.7 CEV R Light Event Capture Example632
Table 11.7 Periodic Relay Checks632
Self-Test633
Table 11.8 Relay Self-Tests634
Table 11.9 Troubleshooting636
Factory Assistance637
- Firmware639
- Table A.1 R200 Series Firmware Revision History639
- Table A.2 R100 Series Firmware Revision History641
- Table A.3 SEL Display Package Revision History645
- Table A.4 SEL Display Package Compatibility with Relay Firmware645
- Table A.5 Devicenet Card Versions646
- Table A.6 EDS File Compatibility646
Appendix A: Firmware, ICD, and Manual Versions646
ICD File646
- Table A.7 SEL-751 ICD File Revision History647
- Table A.8 Instruction Manual Revision History651
- Modbus Register Map653
- Appendix B: Firmware Upgrade Instructions661
Overview661
Upgrade Firmware Using Quickset662
Upgrade Firmware Using a Terminal Emulator666
Figure B.1 Firmware File Transfer Process667
Protocol Verification for Relays with IEC 61850 Option668
Factory Assistance669
- Table C.1 Supported Serial Command Sets671
Appendix C: SEL Communications Processors671
SEL Communications Protocols671
- Table C.2 Compressed ASCII Commands672
- Figure C.1 SEL Communications Processor Star Integration Network673
- Table C.3 SEL Communications Processors Protocol Interfaces674
Figure C.2 Multitiered SEL Communications Processor Architecture674
SEL Communications Processor and Relay Architecture675
- Figure C.3 Enhancing Multidrop Networks with SEL Communications Processors676
- Table C.4 SEL Communications Processor Port 1 Settings677
- Table C.5 SEL Communications Processor Data Collection Automessages677
- Table C.8 Communications Processor METER Region Map with the 2 AVI/4 AFD Card Installed679
- Table C.10 Communications Processor DEMAND Region Map681
- Figure C.5 Unsolicited Write Settings682
- Figure C.6 Setting Remote Analogs RA01 through RA13684
- Overview685
- Table D.1 DNP3 Implementation Levels685
- Table D.2 Selected DNP3 Function Codes687
- Table D.3 DNP3 Access Methods688
- Table D.4 TCP/UDP Selection Guidelines690
- Table D.5 DNP3 Access Methods690
DNP3 in the SEL-751690
- Figure D.1 Application Confirmation Timing with URETRY N = 2691
- Figure D.2 Message Transmission Timing692
- Table D.6 SEL-751 Event Buffer Capacity693
- Table D.7 Port DNP3 Protocol Settings695
- Table D.8 Serial Port DNP3 Modem Settings696
- Table D.9 SEL-751 DNP Object List698
- Table D.10 DNP3 Reference Data Map703
- Table D.11 DNP3 Default Data Map704
- Table D.12 SEL-751 Object 12 Control Operations707
- Figure D.3 Sample Response to SHO DNP Command708
- Figure D.4 Port MAP Command709
- Table D.13 Sample Custom DNP3 AI Map711
- Figure D.7 AI Point Label, Scaling and Deadband in712
- Figure D.8 Sample Custom DNP3 AO Map Settings713
- Figure D.10 Sample Custom DNP3 BO Map Settings714
- Figure D.11 Binary Output Map Entry in AC SEL714
- Table E.1 Modbus Query Fields716
- Table E.2 SEL-751 Modbus Function Codes716
- Table E.3 SEL-751 Modbus Exception Codes717
- Table E.4 01H Read Discrete Output Coil Status Command718
- Table E.5 Responses to 01H Read Discrete Output Coil Query Errors718
- Table E.6 02H Read Input Status Command718
- Table E.7 02H SEL-751 Inputs719
- Table E.10 Responses to 03H Read Holding Register Query Errors720
- Table E.8 Responses to 02H Read Input Query Errors720
- Table E.9 03H Read Holding Register Command720
- Table E.11 04H Read Input Register Command721
- Table E.12 Responses to 04H Read Input Register Query Errors721
- Table E.13 05H Force Single Coil Command721
- Table E.14 01H, 05H SEL-751 Output722
- Table E.15 Responses to 05H Force Single Coil Query Errors724
- Table E.16 06H Preset Single Register Command724
- Table E.17 Responses to 06H Preset Single Register Query Errors725
- Table E.18 08H Loopback Diagnostic Command725
- Table E.19 Responses to 08H Loopback Diagnostic Query Errors725
- Table E.20 10H Preset Multiple Registers Command726
- Table E.21 10H Preset Multiple Registers Query Error Messages726
- Table E.22 60H Read Parameter Information Command726
- Table E.23 60H Read Parameter Descriptor Field Definition727
- Table E.24 60H Read Parameter Conversion Field Definition727
- Table E.25 Responses to 60H Read Parameter Information Query Errors728
- Table E.26 61H Read Parameter Text Command728
- Table E.27 61H Read Parameter Text Query Error Messages729
- Table E.28 62H Read Enumeration Text Command729
- Table E.29 61H Read Parameter Enumeration Text Query Error Messages729
- Table E.30 7Dh Encapsulated Packet with Control Command729
- Table E.31 7Dh Encapsulated Packet Query Errors730
- Table E.32 7Eh NOP Command730
- Table E.33 Modbus Register Labels for Use with SET M Command732
- Table E.34 Modbus Register Map739
Appendix F: IEC 61850 Communications777
Features777
- Table F.1 IEC 61850 Document Set778
IEC 61850 Operation779
- Table F.2 Example IEC 61850 Descriptor Components780
- Table F.4 Buffered Report Control Block Client Access784
- Table F.5 Unbuffered Report Control Block Client Access784
Logical Nodes795
- Table F.21 Logical Device: MET (Metering)807
- Table F.22 Logical Device: con (Remote Control)811
- Table F.23 Logical Device: ANN (Annunciation)812
- Table F.24 Logical Device: CFG (Configuration)818
- Table F.25 PICS for A-Profile Support818
- Table F.26 PICS for T-Profile Support818
Protocol Implementation Conformance Statement818
- Table F.27 MMS Service Supported Conformance819
- Table F.28 MMS Parameter CBB821
- Table F.29 Alternateaccessselection Conformance Statement821
- Table F.30 Variableaccessspecification Conformance Statement822
- Table F.31 Variablespecification Conformance Statement822
- Table F.32 Read Conformance Statement822
- Table F.33 Getvariableaccessattributes Conformance Statement822
- Table F.34 Definenamedvariablelist Conformance Statement822
- Table F.35 Getnamedvariablelistattributes Conformance Statement823
- Table F.36 Deletenamedvariablelist823
- Table F.37 GOOSE Conformance823
- Table F.38 ACSI Basic Conformance Statement824
- Table F.39 ACSI Models Conformance Statement824
ACSI Conformance Statements824
- Table F.40 ACSI Services Conformance Statement825
- Table G.1 IEC 60870-5 Standard Documents829
Appendix I: Synchrophasors829
Overview829
- Table G.2 IEC 60870-5 Enhanced Performance Architecture Model830
- Table G.3 History of IEC 60870-5830
- Table G.4 SEL-751 ASDU Types831
- Table G.5 IEC 60870-5-103 Category Map Settings832
- Table G.6 IEC 60870-5-103 Cause of Transmission833
- Table G.7 IEC 60870-5-103 Information Numbers833
- Table G.8 IEC 60870-5-103 Standard Function Types834
- Table G.9 IEC 60870-5-103 Data Map834
- Table G.10 SEL-751 IEC 60870-5-103 Port Settings837
- Table G.11 SEL-751 Analog Fault Quantities838
IEC 60870-5-103 Documentation840
Figure H.1 Devicenet Card Component Overview841
Features842
Electronic Data Sheet843
Appendix J: MIRROREDBITS Communications845
Overview845
Figure I.1 Phase Reference846
Synchrophasor Measurement846
- Figure I.2 Waveform at Relay Terminals May Have a Phase Shift847
- Figure I.3 Correction of Measured Phase Angle847
- Table I.1 PMU Settings in the SEL-751 for C37.118 Protocol in Global Settings848
Settings for Synchrophasors848
- Table I.2 Synchrophasor Order in Data Stream (Voltages and Currents)850
- Table I.3 User-Defined Analog Values Selected by the NUMANA Setting851
- Table I.4 User-Defined Digital Status Words Selected by the NUMDSW Setting851
- Table I.5 SEL-751 Serial Port Settings for Synchrophasors852
- Table I.6 SEL-751 Ethernet Port Settings for Synchrophasors853
- Figure I.4 TCP Connection854
- Table I.7 Synchrophasor Trigger Relay Word Bits855
- Table I.8 Time Synchronization Relay Word Bits855
- Table I.9 TQUAL Bits Translation to Time Quality856
View Synchrophasors Using the MET PM Command857
Figure I.7 Sample MET PM Command Response858
C37.118 Synchrophasor Protocol858
- Table I.10 Size of a C37.118 Synchrophasor Message859
- Table I.11 Serial Port Bandwidth for Synchrophasors (in Bytes)859
IEEE C37.118 PMU Setting Example860
- Table I.12 Example Synchrophasor Global Settings862
- Table I.13 Example Synchrophasor Logic Settings862
- Table I.14 Example Synchrophasor SEL OGIC Settings862
- Table I.15 Example Synchrophasor Port Settings862
- Table J.865
- Table J.1 Number of MIRRORED BITS Messages for Different Data Rates866
- Table J.2 Positions of the MIRRORED BITS867
- Table J.3 MIRRORED BITS Values for a RXDFLT Setting of 10100111867
- Table J.4 MIRRORED BITS Communications Message Transmission Period869
- Table J.5 MIRRORED BITS Protocol Settings869
- Table K.1 SEL OGIC Relay Word Bits871
- Table K.2 Relay Word Bit Definitions for the SEL-751 Relay876
- Table L.893
- Table L.1 Analog Quantities894
- Table M.1 IP Port Numbers901
Date Code911
Figure 4.80 Close Logic913
Figure 4.98 Counter913
Figure 8.42 Event History914
Figure 8.43 Event Summary914
Table 7.46 SUMMARY Command914

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