Schweitzer Engineering Laboratories SEL-751 - Page 18

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SEL-751 Relay Instruction Manual Date Code 20170927
List of Figures
Figure 4.51 Z0MTA Setting Provides Forward/Reverse Ground Fault Discrimination
in a Low-Impedance Grounded Distribution System ....................................................... 4.69
Figure 4.52 Zero-Sequence Impedance Network for Ground Fault on Feeder 1 .................................... 4.72
Figure 4.53 Wattmetric Element Operation for Ground Fault on Feeder 1............................................. 4.73
Figure 4.54 Load-Encroachment Logic................................................................................................... 4.79
Figure 4.55 High-Impedance Fault Current Levels Depend on Ground Surface Type ........................... 4.81
Figure 4.56 HIF Detection Block Diagram ............................................................................................. 4.83
Figure 4.57 A-Phase Second Harmonic Blocking................................................................................... 4.86
Figure 4.58 Three-Phase Second- and Fifth-Harmonic Blocking Logic................................................. 4.87
Figure 4.59 Thermal Alarm and Trip Logic ............................................................................................ 4.94
Figure 4.60 Thermal Element Current Overload Logic........................................................................... 4.94
Figure 4.61 Undervoltage Element Logic................................................................................................ 4.99
Figure 4.62 Overvoltage Element Logic................................................................................................ 4.100
Figure 4.63 Logic Diagram of the Inverse-Time Undervoltage Element .............................................. 4.101
Figure 4.64 Inverse Time-Undervoltage Element Curves ..................................................................... 4.103
Figure 4.65 Logic Diagram of the Inverse-Time Overvoltage Element ................................................ 4.104
Figure 4.66 Inverse Time-Overvoltage Element Curves ....................................................................... 4.105
Figure 4.67 Synchronism-Check Voltage Window and Slip Frequency Elements................................ 4.106
Figure 4.68 Synchronism-Check Elements ........................................................................................... 4.107
Figure 4.69 Angle Difference Between VP and VS Compensated by Breaker Close Time
(fP < fS and VP Shown as Reference in This Example) ................................................ 4.112
Figure 4.70 Three-Phase Power Elements Logic................................................................................... 4.116
Figure 4.71 Power Elements Operation in the Real/Reactive Power Plane........................................... 4.117
Figure 4.72 Power Factor Elements Logic ............................................................................................ 4.118
Figure 4.73 Loss-of-Potential (LOP) Logic........................................................................................... 4.120
Figure 4.74 Logic Diagram of the Vector Shift Element....................................................................... 4.121
Figure 4.75 Over- and Underfrequency Element Logic ........................................................................ 4.124
Figure 4.76 81R Frequency Rate-of-Change Scheme Logic................................................................. 4.125
Figure 4.77 81RF Characteristics .......................................................................................................... 4.126
Figure 4.78 81RF Fast Rate-of-Change-of-Frequency Logic................................................................ 4.128
Figure 4.79 Trip Logic........................................................................................................................... 4.129
Figure 4.80 Close Logic ........................................................................................................................ 4.132
Figure 4.81 Reclose Supervision Logic (Following Open Interval Time-Out) ..................................... 4.132
Figure 4.82 Reclose Supervision Limit Timer Operation...................................................................... 4.133
Figure 4.83 SEL-751 Relays Installed at Both Ends of a Transmission Line in a
High-Speed Reclose Scheme.......................................................................................... 4.136
Figure 4.84 Reclosing Relay States and General Operation.................................................................. 4.138
Figure 4.85 Reclosing Sequence From Reset to Lockout With Example Settings................................ 4.142
Figure 4.86 Reclose Blocking for Islanded Generator .......................................................................... 4.148
Figure 4.87 Sequence Coordination Between the SEL-751 and a Line Recloser ................................. 4.151
Figure 4.88 Operation of SEL-751 Shot Counter for Sequence Coordination With Line Recloser
(Additional Settings Example 1) .................................................................................... 4.151
Figure 4.89 Operation of SEL-751 Shot Counter for Sequence Coordination With Line Recloser
(Additional Settings Example 2) .................................................................................... 4.153
Figure 4.90 Demand Current Logic Outputs ......................................................................................... 4.154
Figure 4.91 Response of Thermal and Rolling Demand Meters to a Step Input
(Setting DMTC = 15 minutes)........................................................................................ 4.155
Figure 4.92 Voltage VS Applied to Series RC Circuit .......................................................................... 4.156
Figure 4.93 Schematic Diagram of a Traditional Latching Device....................................................... 4.159
Figure 4.94 Logic Diagram of a Latch Switch ...................................................................................... 4.159
Figure 4.95 SEL
OGIC Control Equation Variable/Timers SV01/SV01T–SV32T ................................. 4.160
Figure 4.96 Result of Falling-Edge Operator on a Deasserting Input ................................................... 4.164
Figure 4.97 Example Use of SEL
OGIC Variables/Timers...................................................................... 4.165
Figure 4.98 Counter 01.......................................................................................................................... 4.166
Figure 4.99 Example of the Effects of the Input Precedence ................................................................ 4.167
Figure 4.100 Phase Rotation Setting ....................................................................................................... 4.169
Figure 4.101 Breaker Failure Logic......................................................................................................... 4.175
Figure 4.102 Arc-Flash Instantaneous Overcurrent Element Logic........................................................ 4.176