ARM Cortex-M3 User Manual

Exceptions
5-18 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Figure 5-5 Exception exit timing
ETMINSTAT indicates:
• 3'b010 to show that the ISR has exited. ETMINTNUM shows the number of the
ISR that exited.
• 3'b011 in the cycle after interrupt exit if a previous stacked ISR is being returned
to. ETMINTNUM shows the number of the interrupt that is being returned to.
Note
If a higher priority exception occurs during the stack pop, the processor abandons the
stack pop, rewinds the stack pointer, and services the exception as a tail-chain case.
5.8.2 Returning the processor from an ISR
Exception returns occur when one of the following instructions loads a value of
0xFFFFFFFX into the PC:
• POP/LDM which includes loading the PC
• LDR with PC as a destination
• BX with any register.
CLK
HADDRI[31:0]
HRDATAI[31:0]
HADDRS[31:0]
HRDATAS[31:0]
SP+0 SP+4 SP+8 SP+C
PC xPSR r0 r1 r2 r3 r12 LR
Last instruction fetch of ISR (BX LR)
CURRPRI[7:0]
ETMINSTAT[2:0]
ETMINTNUM[8:0]
000
34
09
010 000 011
FF
000
00
SP+18
SP+1C
SP+10
SP+14
PC
PC+4
PC+8
PC+12
PC+16
I0 I1 I2
I3

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit