ARM Cortex-M3 User Manual

Clocking and Resets
6-4 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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6.2 Resets
The processor has three reset inputs. Table 6-3 describes the reset inputs.
Note
nTRST resets SWJ-DP. If your implementation does not contain SWJ-DP, this reset
must be tied off.
Table 6-3 Reset inputs
Reset input Description
PORESETn Resets the entire processor system with the exception of SWJ-DP
SYSRESETn Resets the entire processor system with the exception of debug logic in the:
• Nested Vectored Interrupt Controller (NVIC)
• Flash Patch and Breakpoint (FPB)
• Data Watchpoint and Trace (DWT)
• Instrumentation Trace Macrocell (ITM)
• AHB-AP.
nTRST SWJ-DP reset

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit