ARM Cortex-M3 User Manual

Memory Protection Unit
9-14 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 9-9 describes the cache policy for memory attribute encoding.
Note
All cache policies presented by HPROT and MEMATTR relate to an outer cache.
Table 9-10 describes the AP encoding.
Table 9-11 describes the XN encoding.
Table 9-9 Cache policy for memory attribute encoding
Memory attribute encoding (AA and BB) Cache policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate
Table 9-10 AP encoding
AP[2:0] Privileged permissions User permissions Descriptions
000 No access No access All accesses generate a permission fault
001 Read/write No access Privileged access only
010 Read/write Read only Writes in user mode generate a permission fault
011 Read/write Read/write Full access
100 Unpredictable Unpredictable Reserved
101 Read only No access Privileged read only
110 Read only Read only Privileged/user read only
111 Read only Read only Privileged/user read only
Table 9-11 XN encoding
XN Description
0 All instruction fetches enabled
1 Instruction fetches disabled

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit