ARM Cortex-M3 User Manual

Trace Port Interface Unit
17-16 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
Figure 17-9 shows the bit assignments of the Integration Test Register bit assignments.
Figure 17-9 Integration Test Register-ITATBCTR0 bit assignments
Table 17-11 describes the bit assignments of the Integration Test Register bit
assignments.
Integration Mode Control Register
The Integration Mode Control Register enables topology detection.
The register address, access type, and Reset state are:
Address
0xE0040F00
Access Read/write
Reset state
0x0
Figure 17-10 shows the bit assignments of the Integration Mode Control Register.
Figure 17-10 Integration Mode Control Register bit assignments
31
0
Reserved
1
ATVALID1
ATVALID2
Table 17-11 Integration Test Register-ITATBCTR0 bit assignments
Bits Field Function
[31:1] - Reserved
[0] ATVALID1, ATVALID2 This bit reads or sets the value of ATVALIDS1 OR-ed with ATVALIDS2.
SBZ
31 0
FIFO test mode
1
2
Integration test mode

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit