ARM Cortex-M3 User Manual

Core Debug
10-2 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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10.1 About core debug
Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the Advanced High-performance Bus (AHB-AP) port, see AHB-AP on
page 11-39. The processor can access these registers directly over the internal Private
Peripheral Bus (PPB).
Table 10-1 shows the core debug registers.
The Debug Fault Status Register is also used for debug purposes. See Debug Fault
Status Register on page 8-38 for more information.
Core debug is an optional component. If core debug is removed then halt mode
debugging is not supported, therefore there is no halt, stepping, or register transfer
functionality. Debug monitor mode is still supported.
10.1.1 Halt mode debugging
The debugger can halt the core by setting the C_DEBUGEN and C_HALT bits of the
Debug Halting Control and Status Register. The core acknowledges when halted by
setting the S_HALT bit of the Debug Halting Control and Status Register.
The core can be single stepped by halting the core, setting the C_STEP bit to 1, and
then clearing the C_HALT bit to 0. The core acknowledges completion of the step and
re-halt by setting the S_HALT bit of the Debug Halting Control and Status Register.
10.1.2 Exiting core debug
The core can exit Halting debug by clearing the C_DEBUGEN bit in the Debug Halting
and Status Register.
Table 10-1 Core debug registers
Address Type Reset Value Description
0xE000EDF0 Read/Write
0x00000000
a
a. Bits 5, 3, 2, 1, 0 are reset by PORESETn. Bit [1] is also reset by SYSRESETn and writing a 1
to the VECTRESET bit of the Application Interrupt and Reset Control Register.
Debug Halting Control and Status Register
0xE000EDF4 Write-only - Debug Core Register Selector Register
0xE000EDF8 Read/Write - Debug Core Register Data Register
0xE000EDFC Read/Write
0x00000000
b
b. Bits 16,17,18,19 are also reset by SYSRESETn and writing a 1 to the VECTRESET bit of the
Application Interrupt and Reset Control Register.
Debug Exception and Monitor Control Register.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit