ARM Cortex-M3 User Manual

AC Characteristics
19-10 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Table 19-16 shows the timing parameters for the test output ports.
Clock uncertainty 50% HTMDHBURST[2:0]
Clock uncertainty 50% HTMDHPROT[3:0]
Clock uncertainty 50% HTMDHWDATA[31:0]
Clock uncertainty 50% HTMDHWRITE
Clock uncertainty 50% HTMDHRDATA[31:0]
Clock uncertainty 50% HTMDHREADY
Clock uncertainty 50% HTMDHRESP[1:0]
Table 19-16 Test output ports timing parameters
Output delay Min. Output delay Max. Signal name
Clock uncertainty 10% SO
Clock uncertainty 10% WSOO
Clock uncertainty 10% WSIO
Table 19-15 HTM interface output ports timing parameters (continued)
Output delay Min. Output delay Max. Signal name

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit