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Embedded Trace Macrocell

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Note

One of the EXTIN inputs to the ETM could be driven from the LOCKUP output from

the core to enable trace capture to stop, or trigger if a lockup condition occurs. The

EXTIN inputs are not synchronized in the ETM. If they are not driven from the ETM

clock, then you must synchronize them outside the ETM.

MAXEXTIN[1:0] Maximum supported external inputs Input FCLK

CGBYPASS Bypass architectural clock gating cell Input FCLK

FIFOFULLEN Enable ETMFIFOFULL Input FCLK

Table 14-2 Miscellaneous configuration inputs (continued)

Name Description Direction Clock domain

Table 14-3 Trace port signals

Name Description Direction Clock domain

ATDATAM[ 7: 0] Eight-bit trace data Output FCLK

ATVAL ID M ATDATA is valid Output FCLK

ATIDM [6:0 ] Trace Source ID Output FCLK

ATREADYM Indicates that the Trace Port is able to accept the Data on ATDATA Input FCLK

AFREADYM Indicates that the ETM FIFO is empty Output FCLK

Table 14-4 Other signals

Name Description Direction Clock domain

FIFOPEEK[9:0] For validation purposes only Output FCLK

FIFOFULL ETM FIFO is full Output FCLK

ETMPWRUP Indicates that the ETM is powered up Output FCLK

ETMTRIGOUT Trigger occurred status signal Output HCLK

ETMDBGRQ Debug request to core Output FCLK

ETMEN ETM traceport enabled Output FCLK

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ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit