Signal Descriptions
A-8 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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A.6 ICode interface
Table A-6 lists the signals of the ICode interface.
Table A-6 ICode interface
Name Direction Description
HADDRI[31:0] Output 32-bit instruction address bus
HTRANSI[1:0] Output Indicates whether the current transfer is IDLE or NONSEQUENTIAL.
HSIZEI[2:0] Output Indicates the size of the instruction fetch. All instruction fetches are 32-bit on
Cortex-M3.
HBURSTI[2:0] Output Indicates if the transfer is part of a burst. All instruction fetches and vector table loads
are performed as SINGLE on Cortex-M3.
HPROTI[3:0] Output Provides information on the access. Always indicates cacheable and non-bufferable
on this bus.
HPROTI[0] = 0 indicates instruction fetch
HPROTI[0] = 1 indicates vector fetch
MEMATTRI[1:0] Output Memory attributes. Always 01 for this bus (non-shareable, allocate).
BRCHSTAT[3:0] Output Provides hint information on the current or coming AHB fetch requests. Conditional
opcodes could be a speculation and subsequently discarded.
0000 No hint
0001 Conditional branch backwards in decode
0010 Conditional branch in decode
0011 Conditional branch in execute
0100 Unconditional branch in decode
0101 Unconditional branch in execute
0110 Reserved
0111 Reserved
1000 Conditional branch in decode taken (cycle after IHTRANS)
1001 ... 1111 Reserved
HRDATAI[31:0] Input Instruction read bus.
HREADYI Input When HIGH indicates that a transfer has completed on the bus. This signal is driven
LOW to extend a transfer.
HRESPI[1:0] Input The transfer response status. OKAY or ERROR.
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