ARM Cortex-M3 User Manual

Core Debug
10-12 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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10.3 Core debug access example
If you want to halt the processor and write a value into one of the registers, perform the
following sequence:
1. Write
0xA05F0003 to the Debug Halting Control and Status register. This enables
debug and halts the core.
2. Wait for the S_HALT bit of the Debug Halting and Status Register to be set. This
indicates that the core is halted.
3. Write the value that you want to be written to the Debug Core Register Data
Register.
4. Write the register number that you want to write to into the Debug Core Register
Selector Register.

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit