ARM Cortex-M3 User Manual

Memory Protection Unit
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 9-5
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Unless HFNMIENA is set, the MPU is not enabled when the exception priority is –1 or
–2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK
is enabled. The HFNMIENA bit enables the MPU when operating with these two
priorities.
The register address, access type, and Reset state are:
Address
0xE000ED94
Access Read/write
Reset state
0x00000000
Figure 9-2 shows the bit assignments of the MPU Control Register.
Figure 9-2 MPU Control Register bit assignments
31 10
Reserved
HFNMIENA
ENABLE
2
PRIVDEFENA
3

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit