ARM Cortex-M3

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Memory Protection Unit

Unrestricted Access Non-Confidential

Unless HFNMIENA is set, the MPU is not enabled when the exception priority is –1 or

–2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK

is enabled. The HFNMIENA bit enables the MPU when operating with these two

priorities.

The register address, access type, and Reset state are:

Address

0xE000ED94

Access Read/write

Reset state

0x00000000

Figure 9-2 shows the bit assignments of the MPU Control Register.

Figure 9-2 MPU Control Register bit assignments

31 10

Reserved

HFNMIENA

ENABLE

PRIVDEFENA

Main Page

Default Chapter5
- Table of Contents5
Preface20
- About this Book20
- Key to Timing Diagram Conventions23
- Feedback25
Chapter 1 Introduction28
- About the Processor28
- Components, Hierarchy, and Implementation30
- Figure 1-1 Cortex-M3 Block Diagram31
- Table37
- Execution Pipeline Stages38
- Figure 1-2 Cortex-M3 Pipeline Stages38
- Prefetch Unit40
- Branch Target Forwarding41
- Store Buffers44
- Product Revisions45
- About the DP46
Chapter 2 Programmer's Model50
- About the Programmer's Model50
- Privileged Access and User Access51
- Registers52
- Figure 2-1 Processor Register Set52
- Table 2-1 Application Program Status Register Bit Assignments54
- Figure 2-2 Application Program Status Register Bit Assignments54
- Figure 2-3 Interrupt Program Status Register Bit Assignments54
- Table 2-2 Interrupt Program Status Register Bit Assignments55
- Table 2-3 Bit Functions of the EPSR56
- Figure 2-4 Execution Program Status Register56
- Data Types58
- Memory Formats59
- Figure 2-5 Little-Endian and Big-Endian Memory Formats60
- Instruction Set Summary61
- Table 2-4 16-Bit Cortex-M3 Instruction Summary61
- Table 2-5 32-Bit Cortex-M3 Instruction Summary64
Chapter 3 System Control73
- Copyright © 2005-2008 ARM Limited. All Rights Reserved73
- Summary of Processor Registers74
- Table 3-1 NVIC Registers74
- Table 3-2 Core Debug Registers74
- Core Debug Registers77
- Table 3-3 Flash Patch Register Summary78
- Table 3-4 DWT Register Summary79
- Table 3-5 ITM Register Summary81
- Table 3-6 AHB-AP Register Summary82
- Table 3-7 Summary of Debug Interface Port Registers82
- Table 3-8 MPU Registers83
- Table 3-9 TPIU Registers84
- Table 3-10 ETM Registers85
Chapter 4 Memory Map89
- About the Memory Map90
- Figure 4-1 Processor Memory Map90
- Table 4-1 Memory Interfaces91
- Table 4-2 Memory Region Permissions92
- Bit-Banding93
- Figure 4-2 Bit-Band Mapping94
- ROM Memory Table95
- Table 4-3 ROM Table95
Chapter 5 Exceptions98
- About the Exception Model98
- Exception Types100
- Table 5-1 Exception Types100
- Exception Priority102
- Table 5-2 Priority-Based Actions of Exceptions102
- Table 5-3 Priority Grouping104
- Privilege and Stacks105
- Pre-Emption107
- Figure 5-1 Stack Contents after Pre-Emption107
- Table 5-4 Exception Entry Steps108
- Figure 5-2 Exception Entry Timing109
- Tail-Chaining110
- Figure 5-3 Tail-Chaining Timing110
- Late-Arriving111
- Figure 5-4 Late-Arriving Exception Timing111
- Exit113
- Table 5-5 Exception Exit Steps113
- Figure 5-5 Exception Exit Timing114
- Table 5-6 Exception Return Behavior115
- Resets116
- Table 5-7 Reset Actions116
- Table 5-8 Reset Boot-Up Behavior117
- Exception Control Transfer120
- Table 5-9 Transferring to Exception Processing120
- Setting up Multiple Stacks121
- Abort Model123
- Table 5-10 Faults124
- Table 5-11 Debug Faults126
- Table 5-12 Fault Status and Fault Address Registers127
- Activation Levels128
- Table 5-13 Privilege and Stack of Different Activation Levels128
- Table 5-14 Exception Transitions128
- Table 5-15 Exception Subtype Transitions129
- Flowcharts130
- Figure 5-6 Interrupt Handling Flowchart130
- Figure 5-7 Pre-Emption Flowchart131
- Figure 5-8 Return from Interrupt Flowchart132
Chapter 6 Clocking and Resets133
- Clocking134
- Table 6-1 Cortex-M3 Processor Clocks134
- Table 6-2 Cortex-M3 Macrocell Clocks134
- Resets136
- Table 6-3 Reset Inputs136
- Cortex-M3 Reset Modes137
- Table 6-4 Reset Modes137
- Figure 6-1 Reset Signals138
- Figure 6-2 Power-On Reset138
- Figure 6-3 Internal Reset Synchronization139
Chapter 7 Power Management141
- About Power Management142
- System Power Management143
- Table 7-1 Supported Sleep Modes143
- Figure 7-1 SLEEPING Power Control Example144
- Figure 7-2 SLEEPDEEP Power Control Example145
- Figure 7-3 WIC Mode Enable Sequence147
- Figure 7-4 Power down Timing Sequence148
- Figure 7-5 PMU, WIC, and Cortex-M3 Interconnect149
Chapter 8 Nested Vectored Interrupt Controller151
- About the NVIC152
- NVIC Programmer's Model153
- Table 8-1 NVIC Registers153
- Figure 8-1 Interrupt Controller Type Register Bit Assignments157
- Table 8-2 Interrupt Controller Type Register Bit Assignments158
- Figure 8-2 Auxiliary Control Register Bit Assignments158
- Table 8-3 Auxiliary Control Register Bit Assignments159
- Figure 8-3 Systick Control and Status Register Bit Assignments159
- Table 8-4 Systick Control and Status Register Bit Assignments160
- Table 8-5 Systick Reload Value Register Bit Assignments161
- Figure 8-4 Systick Reload Value Register Bit Assignments161
- Figure 8-5 Systick Current Value Register Bit Assignments161
- Table 8-6 Systick Current Value Register Bit Assignments162
- Table 8-7 Systick Calibration Value Register Bit Assignments162
- Figure 8-6 Systick Calibration Value Register Bit Assignments162
- Table 8-8 Interrupt Set-Enable Register Bit Assignments164
- Table 8-9 Interrupt Clear-Enable Register Bit Assignments164
- Table 8-10 Interrupt Set-Pending Register Bit Assignments165
- Table 8-11 Interrupt Clear-Pending Registers Bit Assignments166
- Table 8-12 Active Bit Register Bit Assignments166
- Figure 8-7 Interrupt Priority Registers 0-31 Bit Assignments167
- Table 8-13 Interrupt Priority Registers 0-31 Bit Assignments168
- Table 8-14 CPUID Base Register Bit Assignments168
- Figure 8-8 CPUID Base Register Bit Assignments168
- Table 8-15 Interrupt Control State Register Bit Assignments170
- Figure 8-9 Interrupt Control State Register Bit Assignments170
- Table 8-16 Vector Table Offset Register Bit Assignments172
- Figure 8-10 Vector Table Offset Register Bit Assignments172
- Table 8-17 Application Interrupt and Reset Control Register Bit Assignments173
- Figure 8-11 Application Interrupt and Reset Control Register Bit Assignments173
- Figure 8-12 System Control Register Bit Assignments175
- Table 8-18 System Control Register Bit Assignments176
- Table 8-19 Configuration Control Register Bit Assignments177
- Figure 8-13 Configuration Control Register Bit Assignments177
- Table 8-20 System Handler Priority Registers Bit Assignments179
- Figure 8-14 System Handler Priority Registers Bit Assignments179
- Table 8-21 System Handler Control and State Register Bit Assignments180
- Figure 8-15 System Handler Control and State Register Bit Assignments180
- Figure 8-16 Configurable Fault Status Registers Bit Assignments182
- Table 8-22 Memory Manage Fault Status Register Bit Assignments183
- Figure 8-17 Memory Manage Fault Status Register Bit Assignments183
- Figure 8-18 Bus Fault Status Register Bit Assignments184
- Table 8-23 Bus Fault Status Register Bit Assignments185
- Table 8-24 Usage Fault Status Register Bit Assignments186
- Figure 8-19 Usage Fault Status Register Bit Assignments186
- Figure 8-20 Hard Fault Status Register Bit Assignments187
- Table 8-25 Hard Fault Status Register Bit Assignments188
- Table 8-26 Debug Fault Status Register Bit Assignments189
- Figure 8-21 Debug Fault Status Register Bit Assignments189
- Table 8-27 Memory Manage Fault Address Register Bit Assignments190
- Table 8-28 Bus Fault Address Register Bit Assignments191
- Table 8-29 Auxiliary Fault Status Register Bit Assignments192
- Table 8-30 Software Trigger Interrupt Register Bit Assignments192
- Figure 8-22 Software Trigger Interrupt Register Bit Assignments192
- Level Versus Pulse Interrupts193
Chapter 9 Memory Protection Unit196
- About the MPU196
- MPU Programmer's Model197
- Table 9-1 MPU Registers197
- Table 9-2 MPU Type Register Bit Assignments198
- Figure 9-1 MPU Type Register Bit Assignments198
- Figure 9-2 MPU Control Register Bit Assignments199
- Table 9-3 MPU Control Register Bit Assignments200
- Table 9-4 MPU Region Number Register Bit Assignments201
- Figure 9-3 MPU Region Number Register Bit Assignments201
- Table 9-5 MPU Region Base Address Register Bit Assignments202
- Figure 9-4 MPU Region Base Address Register Bit Assignments202
- Table 9-6 MPU Region Attribute and Size Register Bit Assignments203
- Figure 9-5 MPU Region Attribute and Size Register Bit Assignments203
- Table 9-7 MPU Protection Region Size Field204
- MPU Access Permissions207
- Table 9-8 TEX, C, B Encoding207
- Table 9-9 Cache Policy for Memory Attribute Encoding208
- Table 9-10 AP Encoding208
- Table 9-11 XN Encoding208
- MPU Aborts209
- Updating an MPU Region210
- Interrupts and Updating the MPU213
Chapter 10 Core Debug216
- About Core Debug216
- Table 10-1 Core Debug Registers216
- Core Debug Registers217
- Table 10-2 Debug Halting Control and Status Register218
- Figure 10-1 Debug Halting Control and Status Register Bit Assignments218
- Figure 10-2 Debug Core Register Selector Register Bit Assignments220
- Table 10-3 Debug Core Register Selector Register221
- Table 10-4 Debug Exception and Monitor Control Register223
- Figure 10-3 Debug Exception and Monitor Control Register Bit Assignments223
- Core Debug Access Example226
- Using Application Registers in Core Debug227
- Table 10-5 Application Registers for Use in Core Debug227
Chapter 11 System Debug230
- About System Debug230
- System Debug Access231
- Figure 11-1 System Debug Access Block Diagram232
- System Debug Programmer's Model233
- Fpb234
- Table 11-1 FPB Register Summary235
- Table 11-2 Flash Patch Control Register Bit Assignments236
- Figure 11-2 Flash Patch Control Register Bit Assignments236
- Table 11-3 COMP Mapping238
- Figure 11-3 Flash Patch Remap Register Bit Assignments238
- Table 11-4 Flash Patch Remap Register Bit Assignments239
- Figure 11-4 Flash Patch Comparator Registers Bit Assignments239
- Table 11-5 Flash Patch Comparator Registers Bit Assignments240
- Dwt241
- Table 11-6 DWT Register Summary242
- Table 11-7 DWT Control Register Bit Assignments244
- Figure 11-5 DWT Control Register Bit Assignments244
- Table 11-8 DWT Current PC Sampler Cycle Count Register Bit Assignments247
- Table 11-9 DWT CPI Count Register Bit Assignments248
- Figure 11-6 DWT CPI Count Register Bit Assignments248
- Table 11-10 DWT Exception Overhead Count Register Bit Assignments249
- Figure 11-7 DWT Exception Overhead Count Register Bit Assignments249
- Figure 11-8 DWT Sleep Count Register Bit Assignments249
- Table 11-11 DWT Sleep Count Register Bit Assignments250
- Figure 11-9 DWT LSU Count Register Bit Assignments250
- Table 11-12 DWT LSU Count Register Bit Assignments251
- Table 11-13 DWT Fold Count Register Bit Assignments251
- Figure 11-10 DWT Fold Count Register Bit Assignments251
- Table 11-14 DWT Program Counter Sample Register Bit Assignments252
- Table 11-15 DWT Comparator Registers 0-3 Bit Assignments252
- Table 11-16 DWT Mask Registers 0-3 Bit Assignments253
- Figure 11-11 DWT Mask Registers 0-3 Bit Assignments253
- Table 11-17 Bit Functions of DWT Function Registers 0-3254
- Figure 11-12 DWT Function Registers 0-3 Bit Assignments254
- Table 11-18 Settings for DWT Function Registers256
- Itm258
- Table 11-19 ITM Register Summary258
- Table 11-20 ITM Trace Enable Register Bit Assignments260
- Table 11-21 ITM Trace Privilege Register Bit Assignments261
- Figure 11-13 ITM Trace Privilege Register Bit Assignments261
- Table 11-22 ITM Trace Control Register Bit Assignments262
- Figure 11-14 ITM Trace Control Register Bit Assignments262
- Figure 11-15 ITM Integration Write Register Bit Assignments263
- Table 11-23 ITM Integration Write Register Bit Assignments264
- Table 11-24 ITM Integration Read Register Bit Assignments264
- Figure 11-16 ITM Integration Read Register Bit Assignments264
- Table 11-25 ITM Integration Mode Control Register Bit Assignments265
- Table 11-26 ITM Lock Access Register Bit Assignments265
- Figure 11-17 ITM Integration Mode Control Bit Assignments265
- Table 11-27 ITM Lock Status Register Bit Assignments266
- Figure 11-18 ITM Lock Status Register Bit Assignments266
- Ahb-Ap267
- Table 11-28 AHB-AP Register Summary268
- Table 11-29 AHB-AP Control and Status Word Register Bit Assignments269
- Figure 11-19 AHB-AP Control and Status Word Register269
- Table 11-30 AHB-AP Transfer Address Register Bit Assignments270
- Table 11-31 AHB-AP Data Read/Write Register Bit Assignments271
- Table 11-32 AHB-AP Banked Data Register Bit Assignments271
- Table 11-33 AHB-AP Debug ROM Address Register Bit Assignments272
- Table 11-34 AHB-AP ID Register Bit Assignments272
- Figure 11-20 AHB-AP ID Register272
Chapter 12 Bus Interface274
- About Bus Interfaces274
- AMBA 3 Compliance275
- Icode Bus Interface276
- Table 12-1 Instruction Fetches276
- Dcode Bus Interface278
- System Interface279
- Unifying the Code Buses281
- Figure 12-1 Icode/Dcode Multiplexer281
- External Private Peripheral Interface282
- Access Alignment283
- Table 12-2 Bus Mapper Unaligned Accesses283
- Unaligned Accesses that Cross Regions284
- 12.10 Bit-Band Accesses285
- 12.11 Write Buffer286
- 12.12 Memory Attributes287
- Table 12-3 Memory Attributes287
- 12.13 AHB Timing Characteristics288
- Table 12-4 Interface Timing Characteristics288
Chapter 13 Debug Port289
- About the DP290
Chapter 14 Embedded Trace Macrocell292
- About the ETM292
- Figure 14-1 ETM Block Diagram293
- Table 14-1 ETM Core Interface Inputs and Outputs294
- Table 14-2 Miscellaneous Configuration Inputs294
- Table 14-3 Trace Port Signals295
- Table 14-4 Other Signals295
- Table 14-5 Clocks and Resets296
- Table 14-6 APB Interface Signals296
- Data Tracing297
- ETM Resources298
- Table 14-7 Cortex-M3 Resources298
- Trace Output301
- ETM Architecture302
- Figure 14-2 Return from Exception Packet Encoding302
- Table 14-8 Exception Tracing Mapping303
- Figure 14-3 Exception Encoding for Branch Packet304
- ETM Programmer's Model306
- Table 14-9 ETM Registers306
- Table 14-10 Boolean Function Encoding for Events312
- Table 14-11 Resource Identification Encoding313
- Table 14-12 Input Connections313
- Table 14-13 Trigger Output Connections313
Chapter 15 Embedded Trace Macrocell Interface315
- About the ETM Interface316
- CPU ETM Interface Port Descriptions317
- Table 15-1 ETM Interface Ports317
- Branch Status Interface320
- Table 15-2 Branch Status Signal Function320
- Table 15-3 Branches and Stages Evaluated by the Processor321
- Figure 15-1 Conditional Branch Backwards Not Taken322
- Figure 15-2 Conditional Branch Backwards Taken323
- Figure 15-3 Conditional Branch Forwards Not Taken323
- Figure 15-4 Conditional Branch Forwards Taken323
- Figure 15-5 Unconditional Branch Without Pipeline Stalls324
- Figure 15-6 Unconditional Branch with Pipeline Stalls324
- Table 15-4 Example of an Opcode Sequence325
- Figure 15-7 Unconditional Branch in Execute Aligned325
- Figure 15-8 Unconditional Branch in Execute Unaligned325
- Figure 15-9 Example of an Opcode Sequence327
Chapter 16 AHB Trace Macrocell Interface329
- About the AHB Trace Macrocell Interface330
- CPU AHB Trace Macrocell Interface Port Descriptions331
- Table 16-1 AHB Interface Ports331
Chapter 17 Trace Port Interface Unit334
- About the TPIU334
- Figure 17-1 TPIU Block Diagram (Non-ETM Version)335
- Figure 17-2 TPIU Block Diagram (ETM Version)336
- Table 17-1 Trace out Port Signals337
- Table 17-2 ATB Port Signals338
- Table 17-3 Miscellaneous Configuration Inputs338
- Table 17-4 APB Interface339
- TPIU Registers340
- Table 17-5 TPIU Registers340
- Table 17-6 Async Clock Prescaler Register Bit Assignments342
- Figure 17-3 Supported Sync Port Size Register Bit Assignments342
- Figure 17-4 Async Clock Prescaler Register Bit Assignments342
- Table 17-7 Selected Pin Protocol Register Bit Assignments343
- Figure 17-5 Selected Pin Protocol Register Bit Assignments343
- Table 17-8 Formatter and Flush Status Register Bit Assignments344
- Figure 17-6 Formatter and Flush Status Register Bit Assignments344
- Table 17-9 Formatter and Flush Control Register Bit Assignments345
- Figure 17-7 Formatter and Flush Control Register Bit Assignments345
- Table 17-10 Integration Test Register-ITATBCTR2 Bit Assignments347
- Figure 17-8 Integration Test Register-ITATBCTR2 Bit Assignments347
- Table 17-11 Integration Test Register-ITATBCTR0 Bit Assignments348
- Figure 17-9 Integration Test Register-ITATBCTR0 Bit Assignments348
- Figure 17-10 Integration Mode Control Register Bit Assignments348
- Table 17-12 Integration Mode Control Register Bit Assignments349
- Table 17-13 Integration Register : TRIGGER Bit Assignments349
- Figure 17-11 Integration Register : TRIGGER Bit Assignments349
- Table 17-14 Integration Register : FIFO Data 0 Bit Assignments350
- Figure 17-12 Integration Register : FIFO Data 0 Bit Assignments350
- Table 17-15 Integration Register : FIFO Data 1 Bit Assignments351
- Figure 17-13 Integration Register : FIFO Data 1 Bit Assignments351
- Serial Wire Output Connection353
- Figure 17-14 Dedicated Pin Used for TRACESWO353
- Figure 17-15 SWO Shared with TRACEPORT354
- Figure 17-16 SWO Shared with JTAG-TDO354
Chapter 18 Instruction Timing355
- About Instruction Timing356
- Processor Instruction Timings357
- Table 18-1 Instruction Timings357
- Load-Store Timings361
Chapter 19 AC Characteristics363
- Processor Timing Parameters364
- Table 19-1 Miscellaneous Input Ports Timing Parameters364
- Table 19-2 Low Power Input Ports Timing Parameters364
- Table 19-3 Interrupt Input Ports Timing Parameters365
- Table 19-4 AHB Input Ports Timing Parameters365
- Table 19-5 PPB Input Port Timing Parameters366
- Table 19-6 Debug Input Ports Timing Parameters366
- Table 19-7 Test Input Ports Timing Parameters367
- Table 19-8 ETM Input Port Timing Parameters367
- Table 19-9 Miscellaneous Output Ports Timing Parameters367
- Table 19-10 Low Power Output Ports Timing Parameters368
- Table 19-11 AHB Output Ports Timing Parameters368
- Table 19-12 PPB Output Ports Timing Parameters370
- Table 19-13 Debug Interface Output Ports Timing Parameters370
- Table 19-14 ETM Interface Output Ports Timing Parameters371
- Table 19-15 HTM Interface Output Ports Timing Parameters371
- Table 19-16 Test Output Ports Timing Parameters372
Appendix A Signal Descriptions374
- Clocks374
- A.1 Clocks374
- Table A-1 Clock Signals374
- Resets375
- A.2 Resets375
- Table A-2 Reset Signals375
- Miscellaneous376
- A.3 Miscellaneous376
- Table A-3 Miscellaneous Signals376
- Interrupt Interface378
- A.4 Interrupt Interface378
- Table A-4 Interrupt Interface Signals378
- Low Power Interface379
- Table A-5 Low Power Interface Signals379
- Icode Interface380
- Table A-6 Icode Interface380
- Dcode Interface381
- Table A-7 Dcode Interface381
- System Bus Interface382
- Table A-8 System Bus Interface382
- Private Peripheral Bus Interface383
- Table A-9 Private Peripheral Bus Interface383
- ITM Interface384
- Table A-10 ITM Interface384
- AHB-AP Interface385
- Table A-11 AHB-AP Interface385
- ETM Interface386
- Table A-12 ETM Interface386
- AHB Trace Macrocell Interface388
- Table A-13 HTM Interface388
- Test Interface389
- Table A-14 Test Interface389
- WIC Interface390
- A.15 WIC Interface390
- Table A-15 WIC Interface Signals390
Appendix B Revisions391
- Table B-1 Differences between Issue E and Issue F391
- Table B-2 Differences between Issue F and Issue G395

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