ARM Cortex-M3 User Manual

Exceptions
5-36 Copyright © 2005-2008 ARM Limited. All rights reserved. ARM DDI 0337G
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Figure 5-8 Return from interrupt flowchart
Return
Adjust stack, load pipeline
from PC
Set LR, tail-chain to new
interrupt
Pop next register
Execute instructions
Late-arriving
higher priority
interrupt?
Yes
Popped last
register?
Yes
No
No
Read new PC from vector
table
Fill pipeline from PC
Execute instructions

ARM Cortex-M3 Specifications

General

Architecture	ARMv7-M
Instruction Set	Thumb-2
Pipeline Stages	3-stage
Interrupts	Nested Vectored Interrupt Controller (NVIC)
Interrupt Controller	Nested Vectored Interrupt Controller (NVIC)
Memory Protection Unit	Optional
Power Consumption	Varies by implementation
Max Clock Speed	Up to 100 MHz
Debugging	JTAG and Serial Wire Debug (SWD)
Operating Voltage	1.8V to 3.6V
Manufacturing Process	Varies by implementation
Core Type	32-bit