ARM Cortex-M3

Nested Vectored Interrupt Controller
ARM DDI 0337G Copyright © 2005-2008 ARM Limited. All rights reserved. 8-39
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The register address, access type, and Reset state are:
Address
0xE000ED30
Access Read/write-one-to-clear
Reset state
0x00000000
Figure 8-21 shows the bit assignments of the Debug Fault Status Register.
Figure 8-21 Debug Fault Status Register bit assignments
Table 8-26 describes the bit assignments of the Debug Fault Status Register.
31 4 3 2 1 0
Reserved
EXTERNAL
VCATCH
DWTTRAP
BKPT
HALTED
5
Table 8-26 Debug Fault Status Register bit assignments
Bits Field Function
[31:5] - Reserved
[4] EXTERNAL External debug request flag:
1 = EDBGRQ signal asserted
0 = EDBGRQ signal not asserted.
The processor stops on next instruction boundary.
[3] VCATCH Vector catch flag:
1 = vector catch occurred
0 = no vector catch occurred.
When the VCATCH flag is set, a flag in one of the local fault status registers is also set to
indicate the type of fault.